Abstract:
A PFC-PWM controller with a power saving means is disclosed. A built-in current synthesizer generates a bias current in response to feedback voltages sampled from the PWM circuit and the PFC circuit. The bias current modulates the oscillation frequency to further reduce the switching frequencies of the PWM signal and the PFC signal under light-load and zero-load conditions. Thus, power consumption is greatly reduced. The PFC and the PWM switching signals interleave each other, so that power can be transferred more smoothly from the PFC circuit to the PWM circuit. The saturation of the switching components can be avoided by limiting the maximum on-time of the PWM signal. Further, an external resistor is used to start up the PFC-PWM controller and provide an AC template signal for PFC control.
Abstract:
FI over-voltage crowbar provides lightning surge and ESD protection. The crowbar has a clamping transistor, which is driven by a mirror-amplifier. When an input surge voltage is higher than the voltage of a Zener diode, the mirror-amplifier will be switched on and generate an amplified voltage. The amplified voltage works together with a speed-up capacitor easily to switch on the clamping transistor. The mirror-amplifier has an n-transistor and two p-transistors, which provide sufficient headroom for the turn-on of a clamping transistor. The over-voltage crowbar of this invention rapidly drives the clamping transistor to low impedance, thereby achieving a higher sustenance rating for lightning surge and ESD in the integrated circuit.
Abstract:
A fan speed pulse filter is used for a PWM fan. The filter comprises a comparator, a latch circuit and a synchronizer. The fan unit, including a tachometer pulse output, is controlled by a PWM signal for determining the fan speed. By comparing the PWM signal with a reference voltage, the comparator generates a reset signal. The latch circuit, coupled to the comparator and the fan unit, receives the reset signal and the tachometer pulse and outputs a filtered tachometer pulse containing no phantom pulses. Furthermore, a synchronizer generates an output signal without interruption when the PWM signal is switched off.
Abstract:
A wall control interface for power management includes a transmitting circuit that generates a switching signal to control a switch and achieve a phase modulation to a power line signal in response to a transmitting-data. A receiving circuit is coupled to detect the phase of the power line signal for generating a data signal and a receiving-data in response to the phase of the power line signal. The receiving circuit further generates a control signal to control power of a load in accordance with the data signal or the receiving-data. The phase modulation is achieved by controlling a turn-on angle of the power line signal. The switch remains in a turn-on state during the normal condition, which achieves good power and low current harmonic. The phase modulation is only performed during the communication of the power management.
Abstract:
A switching controller having switching frequency hopping for a power converter includes a first oscillator generating a pulse signal and a maximum duty-cycle signal for determining a switching frequency of a switching signal, a pattern generator having a second oscillator and generating a digital pattern code in response to a clock signal, a programmable capacitor coupled to the pattern generator and the first oscillator for modulating the switching frequency of the switching signal in response to the digital pattern code, and a PWM circuit coupled to the first oscillator for generating the switching signal in accordance with the maximum duty-cycle signal. A maximum on-time of the switching signal is limited by the maximum duty-cycle signal. The switching signal is utilized to switch a transformer of the power converter.
Abstract:
A structure of an electrostatic discharge (ESD) device integrated with a pad is provided. The ESD device is integrated with the pad and formed under the pad. By using the area under the pad, the ESD device does not occupy additional space of an integrated circuit. Furthermore, since the pad is a large, plate, and ideal conductor, the connected pad and the ESD device are capable of distributing current in the ESD device averagely.
Abstract:
A high voltage LDMOS transistor according to the present invention includes at least one P-field block in the extended drain region of the N-well. The P-field blocks form junction-fields in the N-well for equalizing the capacitance of parasitic capacitors between the drain region and the source region and fully deplete the drift region before breakdown occurs. A higher breakdown voltage is therefore achieved and the N-well having a higher doping density is thus allowed. The source region and P-field blocks enclose the drain region, which makes the LDMOS transistor self-isolated.
Abstract:
A structure of an electrostatic discharge (ESD) device integrated with a pad is provided. The ESD device is integrated with the pad and formed under the pad. By using the area under the pad, the ESD device does not occupy additional space of an integrated circuit. Furthermore, since the pad is a large, plate, and ideal conductor, the connected pad and the ESD device are capable of distributing current in the ESD device averagely.
Abstract:
A power-mode controlled power converter is capable of supplying a constant output voltage and output current. A PWM controller generates a PWM signal in response to a voltage sampled from a transformer auxiliary winding. A programmable current-sink and a detection resistor compensate for a voltage drop of an output rectifier. A low-pass filter integrates a switching-current voltage to an average-current signal. An attenuator produces an input-voltage signal from a line-voltage input signal. The PWM controller multiplies the average-current signal with the input-voltage signal to generate a power-control signal. An error-amplifier compares the power-control signal with a power-reference voltage to generate a limit voltage. The limit voltage controls the power delivered from a primary-side circuit to a secondary-side circuit of the power-mode controlled power converter. Since the power-reference voltage varies in proportional to output voltage variations, a constant output current is therefore achieved.
Abstract:
A close-loop PWM controller for a primary-side controlled power converter is provided. A voltage-waveform detector produces a voltage-feedback signal and a discharge-time signal. A current-waveform detector generates a current-waveform signal by measuring a primary-side switching current. An integrator generates a current-feedback signal by integrating the current-waveform signal with the discharge-time signal. A time constant of the integrator is correlated with a switching period of the switching signal, therefore the current-feedback signal is proportional to the output current of the power converter. The close-loop PWM controller further including a voltage-loop error amplifier and a current-loop error amplifier. A PWM circuit and comparators control the pulse width of the switching signal in response to the outputs of the voltage-loop error amplifier and the current-loop error amplifier. The output voltage and the maximum output current of the power converter are therefore regulated.