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11.发明授权Microprocessor cache memory way prediction based on the way of a previous memory read 失效基于先前存储器读取方式的微处理器缓存存储器方式预测
公开(公告)号：US5822756A
公开(公告)日：1998-10-13
申请号：US839158
申请日：1997-04-23
申请人： Gary W. Thome , Jens K. Ramsey
发明人： Gary W. Thome , Jens K. Ramsey
IPC分类号： G06F12/08
CPC分类号： G06F12/0864 , G06F2212/6082
摘要： In a microcomputer system using a multiple-way cache memory subsystem, the way of the next microprocessor operation is predicted, and either the output enables of the cache are predriven, or, in a single-bank multiple-way cache, the address bit which acts as a way selection is appropriately set. The way prediction used is based not on the address being accessed in the cache, but instead on the last processor code read, or the last processor code or data read. This permits the cache memory subsystem to respond more quickly on hits to the appropriate way, and also allows for slower cache memories to be used without reducing performance.
摘要翻译： 在使用多路缓存存储器子系统的微计算机系统中，预测下一个微处理器操作的方式，并且高速缓存的输出使能被预先驱动，或者在单行多路缓存中，地址位 作为方式选择的适当设定。 所使用的预测方式不是基于缓存中访问的地址，而是基于最后一个处理器代码读取，或最后一个处理器代码或数据读取。 这允许高速缓存存储器子系统以适当的方式更快地响应命中，并且还允许使用较慢的高速缓冲存储器而不降低性能。
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公开(公告)号：US5822571A
公开(公告)日：1998-10-13
申请号：US659142
申请日：1996-06-05
CPC分类号： G06F13/405
摘要： Data is transmitted between a first device and a second device connected by the communications channel in a computer system. The first device generates a first clock and the second device generates a second clock. The first clock is provided to the second device and the second clock is provided to the first device. Data received by the first device over the communications channel from the second device is synchronized to the first clock. The receiving logic in the first device includes a first-in-first-out buffer The received data is stored in a first-in-first-out buffer until the data is synchronized to the first clock. The first and second clocks have the same frequency.
摘要翻译： 在计算机系统中，通过通信信道连接的第一设备和第二设备之间传送数据。 第一设备产生第一时钟，第二设备产生第二时钟。 将第一时钟提供给第二设备，并且将第二时钟提供给第一设备。 由第一设备通过通信信道从第二设备接收的数据被同步到第一时钟。 第一设备中的接收逻辑包括先进先出缓冲器。接收到的数据被存储在先进先出缓冲器中，直到数据与第一时钟同步。 第一和第二个时钟具有相同的频率。
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13.发明授权System having a plurality of posting queues associated with different types of write operations for selectively checking one queue based upon type of read operation 失效具有与不同类型的写入操作相关联的多个发布队列的系统，用于基于读取操作的类型选择性地检查一个队列
公开(公告)号：US5634073A
公开(公告)日：1997-05-27
申请号：US324246
申请日：1994-10-14
CPC分类号： G06F12/0831 , G06F13/1605 , G06F13/1642 , G06F13/1694
摘要： A memory controller which provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI to memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI to memory queue is to the same address as the read operation of the processor. If so, the read operation is not executed until the PCI memory queue is cleared of the write. To resolve the problem of aborting a Memory Read Multiple operation, an abort signal from the PCI bus interface is received and as soon thereafter as can be done the read ahead cycle is terminated, even though the read ahead cycle has not fully completed. The memory controller has improved prediction rules based on whether the cycle is coming from the processor or is coming from the PCI bus to allow more efficient precharging when PCI bus cycles are used. The memory controller is highly programmable for multiple speeds and types of processors and several speeds of memory devices. The memory controller includes a plurality of registers that specify number of clock periods for the particular portions of a conventional DRAM cycle which are used to control state machine operations.
摘要翻译： 存储器控制器，其在处理器和PCI总线与存储器系统之间提供一系列队列。 内存一致性以两种不同的方式保持。 在PCI总线接受任何读操作之前，两个发送队列都必须为空。 内容可寻址存储器（CAM）被用作PCI到存储器队列。 当处理器执行读取请求时，检查CAM以确定PCI到存储器队列中的待处理写入操作之一是否与处理器的读取操作相同。 如果是这样，则在PCI存储器队列清除写入之前，不执行读取操作。 为了解决中止“内存读取多个”操作的问题，接收到来自PCI总线接口的中断信号，并且尽快完成读取前一周期，即使前面的读取周期尚未完全完成。 存储器控制器基于该周期是来自处理器还是来自PCI总线来改进预测规则，以在使用PCI总线周期时允许更有效的预充电。 存储器控制器是高度可编程的，适用于多种速度和类型的处理器和几种存储器件的速度。 存储器控制器包括多个寄存器，其指定用于控制状态机操作的常规DRAM周期的特定部分的时钟周期数。
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14.发明授权
公开(公告)号：US5446863A
公开(公告)日：1995-08-29
申请号：US168718
申请日：1993-12-16
CPC分类号： G06F12/0835 , G06F12/0811 , G06F13/161
摘要： A method and apparatus for reducing the snooping requirements of a cache system and for reducing latency problems in a cache system. When a snoop access occurs to the cache, and if snoop control logic determines that the previous snoop access involved the same memory location line, then the snoop control logic does not direct the cache to snoop this subsequent access. This eases the snooping burden of the cache and thus increases the efficiency of the processor working out of the cache during this time. When a multilevel cache system is implemented, the snoop control logic directs the cache to snoop certain subsequent accesses to a previously snooped line in order to prevent cache coherency problems from arising. Latency reduction logic which reduces latency problems in the snooping operation of the cache is also included. After every processor read that is transmitted beyond the cache, i.e., cache read misses, the logic gains control of the address inputs of the cache for snooping purposes. The cache no longer needs its address bus for the read cycle and thus the read operation continues unhindered. In addition, the cache is prepared for an upcoming snoop cycle.
摘要翻译： 一种用于减少缓存系统的窥探需求并减少缓存系统中的延迟问题的方法和装置。 当高速缓存发生窥探访问时，如果侦听控制逻辑确定先前的侦听访问涉及同一内存位置行，则侦听控制逻辑不会引导高速缓存窥探此后续访问。 这缓解了缓存的窥探负担，从而提高了在此期间从高速缓存中工作的处理器的效率。 当实现多级缓存系统时，监听控制逻辑引导高速缓存窥探对先前侦听行的某些后续访问，以防止高速缓存一致性问题出现。 还包括减少高速缓存的窥探操作中的延迟问题的延迟降低逻辑。 在每个超出高速缓存的处理器读取，即高速缓存读取未命中之后，逻辑增益用于高速缓存的地址输入的控制用于窥探目的。 缓存不再需要其地址总线用于读取周期，因此读取操作不受阻碍地继续。 此外，高速缓存准备好即将到来的窥探周期。
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15.发明授权Cache memory system which snoops an operation to a first location in a cache line and does not snoop further operations to locations in the same line 失效高速缓冲存储器系统，其将操作窥探到高速缓存行中的第一位置，并且不会进一步操作到同一行中的位置
公开(公告)号：US5325503A
公开(公告)日：1994-06-28
申请号：US839853
申请日：1992-02-21
IPC分类号： G06F12/08 , G06F13/16 , G06F13/000
CPC分类号： G06F12/0835 , G06F12/0811 , G06F13/161
摘要： A method and apparatus for reducing the snooping requirements of a cache system and for reducing latency problems in a cache system. When a snoop access occurs to the cache, and if snoop control logic determines that the previous snoop access involved the same memory location line, then the snoop control logic does not direct the cache to snoop this subsequent access. This eases the snooping burden of the cache and thus increases the efficiency of the processor working out of the cache during this time. When a multilevel cache system is implemented, the snoop control logic directs the cache to snoop certain subsequent accesses to a previously snooped line in order to prevent cache coherency problems from arising. Latency reduction logic which reduces latency problems in the snooping operation of the cache is also included. After every processor read that is transmitted beyond the cache, i.e., cache read misses, the logic gains control of the address inputs of the cache for snooping purposes. The cache no longer needs its address bus for the read cycle and thus the read operation continues unhindered. In addition, the cache is prepared for an upcoming snoop cycle.
摘要翻译： 一种用于减少缓存系统的窥探需求并减少缓存系统中的延迟问题的方法和装置。 当高速缓存发生窥探访问时，如果侦听控制逻辑确定先前的侦听访问涉及同一内存位置行，则侦听控制逻辑不会引导高速缓存窥探此后续访问。 这缓解了缓存的窥探负担，从而提高了在此期间从高速缓存中工作的处理器的效率。 当实现多级缓存系统时，监听控制逻辑引导高速缓存窥探对先前侦听行的某些后续访问，以防止高速缓存一致性问题出现。 还包括减少高速缓存的窥探操作中的延迟问题的延迟降低逻辑。 在每个超出高速缓存的处理器读取，即高速缓存读取未命中之后，逻辑增益用于高速缓存的地址输入的控制用于窥探目的。 缓存不再需要其地址总线用于读取周期，因此读取操作不受阻碍地继续。 此外，高速缓存准备好即将到来的窥探周期。
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16.发明授权Computer system controller and method with processor write posting hold off on PCI master memory request 失效具有处理器写入寄存功能的计算机系统控制器和方法在PCI主存储器请求中保持不变公开(公告)号：US06209067B1
公开(公告)日：2001-03-27
申请号：US08566514
申请日：1995-12-04
IPC分类号： G06F1336
CPC分类号： G06F13/1605 , G06F12/0831 , G06F13/1642 , G06F13/1694
摘要： A computer system including a memory controller provides a series of queues between a processor and a peripheral component interconnect (PCI) bus and a memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A write posting queue for processor to PCI writes must be flushed before a PCI device can access memory. If the queue is not empty when the PCI device requests a memory read, the PCI device is forced to retry the operation while the write posting queue is flushed. Also, while the queue is flushed, the processor is prevented from further posting to the queue. A timer provides a further temporary time that the processor is precluded from posting to allow enough time for the PCI master to retry the operation.
摘要翻译： 包括存储器控制器的计算机系统在处理器与外围部件互连（PCI）总线和存储器系统之间提供一系列的队列。 内存一致性以两种不同的方式保持。 在PCI总线接受任何读操作之前，两个发送队列都必须为空。 在PCI设备可以访问内存之前，必须刷新处理器到PCI写入的写入队列。 如果PCI设备请求存储器读取队列不为空，则在刷新写入过帐队列时，强制PCI设备重试该操作。 此外，当刷新队列时，防止处理器进一步发布到队列。 定时器提供进一步的临时时间，使处理器不被发布以允许足够的时间使PCI主机重试该操作。
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17.发明授权Method of preventing cache corruption during microprocessor pipelined burst operations 失效在微处理器流水线突发操作期间防止高速缓存损坏的方法
公开(公告)号：US5781925A
公开(公告)日：1998-07-14
申请号：US567030
申请日：1995-12-04
CPC分类号： G06F12/0879 , G06F12/0859
摘要： In a microcomputer system implementing cache memory, the microprocessor can execute back-to-back pipelined burst operations without corrupting the internal address of the cache memory. The address strobe from the processor is blocked by the cache memory controller, allowing a burst operation to complete from or to the cache memories before the second address is strobed into the cache.
摘要翻译： 在实现高速缓冲存储器的微计算机系统中，微处理器可以执行背靠背流水线突发操作，而不会破坏高速缓冲存储器的内部地址。 来自处理器的地址选通脉冲被高速缓存存储器控制器阻挡，允许突发操作在第二地址被选通到高速缓存之前从高速缓存存储器完成。
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