公开(公告)号：US06209067B1

公开(公告)日：2001-03-27

申请号：US08566514

申请日：1995-12-04

申请人： Michael J. Collins ,  Michael P. Moriarty ,  John E. Larson ,  Jens K. Ramsey

发明人： Michael J. Collins ,  Michael P. Moriarty ,  John E. Larson ,  Jens K. Ramsey

IPC分类号： G06F1336

CPC分类号： G06F13/1605 ,  G06F12/0831 ,  G06F13/1642 ,  G06F13/1694

摘要： A computer system including a memory controller provides a series of queues between a processor and a peripheral component interconnect (PCI) bus and a memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A write posting queue for processor to PCI writes must be flushed before a PCI device can access memory. If the queue is not empty when the PCI device requests a memory read, the PCI device is forced to retry the operation while the write posting queue is flushed. Also, while the queue is flushed, the processor is prevented from further posting to the queue. A timer provides a further temporary time that the processor is precluded from posting to allow enough time for the PCI master to retry the operation.

摘要翻译： 包括存储器控制器的计算机系统在处理器与外围部件互连（PCI）总线和存储器系统之间提供一系列的队列。 内存一致性以两种不同的方式保持。 在PCI总线接受任何读操作之前，两个发送队列都必须为空。 在PCI设备可以访问内存之前，必须刷新处理器到PCI写入的写入队列。 如果PCI设备请求存储器读取队列不为空，则在刷新写入过帐队列时，强制PCI设备重试该操作。 此外，当刷新队列时，防止处理器进一步发布到队列。 定时器提供进一步的临时时间，使处理器不被发布以允许足够的时间使PCI主机重试该操作。

公开(公告)号：US5938739A

公开(公告)日：1999-08-17

申请号：US811587

申请日：1997-03-05

申请人： Michael J. Collins ,  Gary W. Thome ,  Michael P. Moriarty ,  Jens K. Ramsey ,  John E. Larson

发明人： Michael J. Collins ,  Gary W. Thome ,  Michael P. Moriarty ,  Jens K. Ramsey ,  John E. Larson

IPC分类号： G06F12/08 ,  G06F13/16 ,  G06F13/00 ,  G06F13/14

CPC分类号： G06F12/0831 ,  G06F13/1605 ,  G06F13/1642 ,  G06F13/1694

摘要： A memory controller which provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI to memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI to memory queue is to the same address as the read operation of the processor. If so, the read operation is not executed until the PCI memory queue is cleared of the write. To resolve the problem of aborting a Memory Read Multiple operation, an abort signal from the PCI bus interface is received and as soon thereafter as can be done the read ahead cycle is terminated, even though the read ahead cycle has not fully completed. The memory controller has improved prediction rules based on whether the cycle is coming from the processor or is coming from the PCI bus to allow more efficient precharging when PCI bus cycles are used. The memory controller is highly programmable for multiple speeds and types of processors and several speeds of memory devices.

摘要翻译： 存储器控制器，其在处理器和PCI总线与存储器系统之间提供一系列队列。 内存一致性以两种不同的方式保持。 在PCI总线接受任何读操作之前，两个发送队列都必须为空。 内容可寻址存储器（CAM）被用作PCI到存储器队列。 当处理器执行读取请求时，检查CAM以确定PCI到存储器队列中的待处理写入操作之一是否与处理器的读取操作相同。 如果是这样，则在PCI存储器队列清除写入之前，不执行读取操作。 为了解决中止“内存读取多个”操作的问题，接收到来自PCI总线接口的中断信号，并且尽快完成读取前一周期，即使前面的读取周期尚未完全完成。 存储器控制器基于该周期是来自处理器还是来自PCI总线来改进预测规则，以在使用PCI总线周期时允许更有效的预充电。 存储器控制器是高度可编程的，适用于多种速度和类型的处理器和几种存储器件的速度。

公开(公告)号：US5634073A

公开(公告)日：1997-05-27

申请号：US324246

申请日：1994-10-14

申请人： Michael J. Collins ,  Gary W. Thome ,  Michael P. Moriarty ,  Jens K. Ramsey ,  John E. Larson

发明人： Michael J. Collins ,  Gary W. Thome ,  Michael P. Moriarty ,  Jens K. Ramsey ,  John E. Larson

IPC分类号： G06F12/08 ,  G06F13/16 ,  G06F13/00

CPC分类号： G06F12/0831 ,  G06F13/1605 ,  G06F13/1642 ,  G06F13/1694

摘要： A memory controller which provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI to memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI to memory queue is to the same address as the read operation of the processor. If so, the read operation is not executed until the PCI memory queue is cleared of the write. To resolve the problem of aborting a Memory Read Multiple operation, an abort signal from the PCI bus interface is received and as soon thereafter as can be done the read ahead cycle is terminated, even though the read ahead cycle has not fully completed. The memory controller has improved prediction rules based on whether the cycle is coming from the processor or is coming from the PCI bus to allow more efficient precharging when PCI bus cycles are used. The memory controller is highly programmable for multiple speeds and types of processors and several speeds of memory devices. The memory controller includes a plurality of registers that specify number of clock periods for the particular portions of a conventional DRAM cycle which are used to control state machine operations.

摘要翻译： 存储器控制器，其在处理器和PCI总线与存储器系统之间提供一系列队列。 内存一致性以两种不同的方式保持。 在PCI总线接受任何读操作之前，两个发送队列都必须为空。 内容可寻址存储器（CAM）被用作PCI到存储器队列。 当处理器执行读取请求时，检查CAM以确定PCI到存储器队列中的待处理写入操作之一是否与处理器的读取操作相同。 如果是这样，则在PCI存储器队列清除写入之前，不执行读取操作。 为了解决中止“内存读取多个”操作的问题，接收到来自PCI总线接口的中断信号，并且尽快完成读取前一周期，即使前面的读取周期尚未完全完成。 存储器控制器基于该周期是来自处理器还是来自PCI总线来改进预测规则，以在使用PCI总线周期时允许更有效的预充电。 存储器控制器是高度可编程的，适用于多种速度和类型的处理器和几种存储器件的速度。 存储器控制器包括多个寄存器，其指定用于控制状态机操作的常规DRAM周期的特定部分的时钟周期数。

公开(公告)号：US5781925A

公开(公告)日：1998-07-14

申请号：US567030

申请日：1995-12-04

申请人： John E. Larson ,  Jens K. Ramsey ,  Jeffrey C. Stevens ,  Michael J. Collins

发明人： John E. Larson ,  Jens K. Ramsey ,  Jeffrey C. Stevens ,  Michael J. Collins

IPC分类号： G06F12/08 ,  G06F12/16

CPC分类号： G06F12/0879 ,  G06F12/0859

摘要： In a microcomputer system implementing cache memory, the microprocessor can execute back-to-back pipelined burst operations without corrupting the internal address of the cache memory. The address strobe from the processor is blocked by the cache memory controller, allowing a burst operation to complete from or to the cache memories before the second address is strobed into the cache.

摘要翻译： 在实现高速缓冲存储器的微计算机系统中，微处理器可以执行背靠背流水线突发操作，而不会破坏高速缓冲存储器的内部地址。 来自处理器的地址选通脉冲被高速缓存存储器控制器阻挡，允许突发操作在第二地址被选通到高速缓存之前从高速缓存存储器完成。

公开(公告)号：US07120758B2

公开(公告)日：2006-10-10

申请号：US10365018

申请日：2003-02-12

申请人： Phillip M. Jones ,  Robert A. Lester ,  Jens K. Ramsey ,  William J. Walker ,  John E. Larson ,  James Andre ,  Paul Rawlins

发明人： Phillip M. Jones ,  Robert A. Lester ,  Jens K. Ramsey ,  William J. Walker ,  John E. Larson ,  James Andre ,  Paul Rawlins

IPC分类号： G06F12/00 ,  G06F3/00

CPC分类号： G06F13/1673

摘要： Method and apparatus for improving processor performance. In some embodiments, processing speed may be improved by reusing data stored in a buffer during an initial request by subsequent requests. Assignment of temporary storage buffers in a controller may be made to allow for the potential for reuse of the data. Further, a hot buffer may be designated to allow for reuse of the data stored in the hot buffer. On subsequent requests, data stored in the hot buffer may be sent to a requesting device without re-retrieving the data from memory.

摘要翻译： 提高处理器性能的方法和装置。 在一些实施例中，可以通过在初始请求期间通过后续请求重用存储在缓冲器中的数据来改善处理速度。 控制器中的临时存储缓冲区的分配可以做出以允许数据重用的潜力。 此外，可以指定热缓冲器以允许重新使用存储在热缓冲器中的数据。 在随后的请求中，存储在热缓冲器中的数据可以被发送到请求设备而不从存储器重新检索数据。

公开(公告)号：US5835948A

公开(公告)日：1998-11-10

申请号：US324016

申请日：1994-10-14

申请人： Sompong P. Olarig ,  Jens K. Ramsey ,  Michael J. Collins

发明人： Sompong P. Olarig ,  Jens K. Ramsey ,  Michael J. Collins

IPC分类号： G06F12/08

CPC分类号： G06F12/0879 ,  G06F12/0859

摘要： In a microcomputer system implementing cache memory, a multiple-way cache is implemented in a single-bank memory. Instead of using chip output enables on a separate physical chip for each way of the multiple-way cache, an address line of a single bank of memory is used to select between ways. In this way, fewer parts can be used, and a single-bank memory can be used for a multiple-way cache.

摘要翻译： 在实现高速缓冲存储器的微计算机系统中，在单行存储器中实现多路高速缓存。 代替使用芯片输出，可以在多路缓存的每种方式的单独物理芯片上实现，单个存储器的地址线用于在各种方式之间进行选择。 以这种方式，可以使用更少的部件，并且单行存储器可以用于多路缓存。

公开(公告)号：US5699550A

公开(公告)日：1997-12-16

申请号：US323260

申请日：1994-10-14

申请人： Jens K. Ramsey

发明人： Jens K. Ramsey

IPC分类号： G06F12/08

CPC分类号： G06F12/0802

摘要： In a microcomputer system implementing a cache memory subsystem, the cache performance on write allocation cycles is improved. When the processor writes to a line of the cache memory that results in a cache tag miss, after the processor write operation is suspended, the data is allocated from main memory into the cache memory. During this main memory read, however, instead of setting the state of the line of memory to unmodified, its state is set to modified. On the subsequent processor read operation, a cycle is saved because the modified bit does not have to be changed from unmodified to modified.

摘要翻译： 在实现高速缓存存储器子系统的微计算机系统中，提高了写入分配周期的高速缓存性能。 当处理器写入高速缓存存储器的一行导致高速缓存标签未命中时，在处理器写入操作被暂停之后，数据从主存储器分配到高速缓冲存储器中。 然而，在该主存储器读取期间，不是将存储器行的状态设置为未修改，而是将其状态设置为修改。 在随后的处理器读取操作中，保存一个周期，因为修改的位不必从未修改更改为修改。

公开(公告)号：US5426765A

公开(公告)日：1995-06-20

申请号：US227303

申请日：1994-04-13

申请人： Jeffrey C. Stevens ,  Mike T. Jackson ,  Roger E. Tipley ,  Jens K. Ramsey ,  Sompong Olarig ,  Philip C. Kelly

发明人： Jeffrey C. Stevens ,  Mike T. Jackson ,  Roger E. Tipley ,  Jens K. Ramsey ,  Sompong Olarig ,  Philip C. Kelly

IPC分类号： G06F12/08 ,  G06F13/18 ,  G06F12/00

CPC分类号： G06F12/0831 ,  G06F13/18

摘要： A method for arbitrating between processor and host bus snoop accesses to a cache subsystem in a multiprocessor system where the processor does not allow for processor cycle aborts. When a processor access and a snoop access both occur and no tag access or tag modify cycle is currently being performed, the snoop access is given priority over the processor access. After an initial arbitration, if any, the processor and snoop accesses alternate tag access if both processor and snoop accesses are active. This balances any wait states incurred between the processor and the host bus and ensures that neither bus is locked out by continual accesses by the other. In addition, tag modify cycles are generally run immediately after the tag access cycles that initiate them.

摘要翻译： 一种用于在处理器不允许处理器周期中止的多处理器系统中的处理器和主机总线窥探访问缓存子系统之间进行仲裁的方法。 当处理器访问和窥探访问都发生，并且当前没有执行标签访问或标签修改周期时，侦听访问被优先于处理器访问。 在初始仲裁（如果有的话）之后，如果处理器和侦听访问都处于活动状态，则处理器和侦听器访问备用标签访问。 这将平衡处理器和主机总线之间发生的任何等待状态，并确保总线不被另一个的连续访问锁定。 此外，标签修改周期通常在启动它们的标签访问周期之后立即运行。

公开(公告)号：US5872939A

公开(公告)日：1999-02-16

申请号：US658485

申请日：1996-06-05

申请人： Jens K. Ramsey ,  Alan L. Goodrum ,  Paul R. Culley

发明人： Jens K. Ramsey ,  Alan L. Goodrum ,  Paul R. Culley

IPC分类号： G06F13/36 ,  G06F13/362 ,  G06F13/364 ,  G06F13/00

CPC分类号： G06F13/364

摘要： Access to a bus in a computer system having a CPU and bus devices capable of running cycles on a bus is controlled by an arbiter. The arbiter grants access to the bus according to an arbitration scheme that depends on whether a request for the bus is pending from the CPU, in which a first arbitration scheme arbitrates between the bus devices, and wherein a second arbitration scheme arbitrates between the CPU and at least one other bus device if the CPU request is present.

摘要翻译： 具有能够在总线上运行循环的CPU和总线设备的计算机系统中的总线的访问由仲裁器控制。 仲裁器根据仲裁方案授予对总线的访问，该仲裁方案取决于来自CPU的总线请求是否等待，其中第一仲裁方案在总线设备之间进行仲裁，并且其中第二仲裁方案在CPU和 如果存在CPU请求，则至少另外一个总线设备。

公开(公告)号：US5813022A

公开(公告)日：1998-09-22

申请号：US703927

申请日：1996-08-28

申请人： Jens K. Ramsey ,  Jeffrey C. Stevens ,  Michael E. Tubbs ,  Charles J. Stancil

发明人： Jens K. Ramsey ,  Jeffrey C. Stevens ,  Michael E. Tubbs ,  Charles J. Stancil

IPC分类号： G06F1/32 ,  G06F12/08 ,  G06F12/00

CPC分类号： G06F1/3215 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3268 ,  G06F1/3275 ,  G06F12/0802 ,  G06F12/0811 ,  G06F12/0833 ,  G06F9/30083 ,  G06F2212/1028 ,  Y02B60/1217 ,  Y02B60/1225 ,  Y02B60/1228 ,  Y02B60/1246

摘要： A circuit for placing an external or L2 cache memory into low power mode in response to certain special cycles executed by the microprocessor. In particular, the special cycles are the stop grant acknowledge special cycle and the halt special cycle. The microprocessor executes the stop grant acknowledge special cycle in response to a request by the computer system to slow down its clock. This request is asserted by the computer system if the system has been idle for a predetermined period of time. The halt special cycle is generated by the microprocessor when a HALT instruction is executed. The stop grant acknowledge and halt special cycles place the microprocessor into a low power state. Since the microprocessor is in low power mode, the L2 cache memory is also placed into low power mode for further power conservation. The L2 cache memory is implemented either with synchronous or asynchronous static random access memories (SRAMs). To place a synchronous SRAM into low power mode, its address strobe input is asserted while its chip select input is deasserted. For an asynchronous SRAM, deasserting its chip select input causes the SRAM to transition into low power mode.

摘要翻译： 用于响应于微处理器执行的某些特殊周期将外部或L2高速缓冲存储器置于低功率模式的电路。 特别是特殊周期是停止授权确认特殊周期和停止特殊周期。 微处理器响应于计算机系统减慢其时钟的请求而执行停止许可确认特殊周期。 如果系统已经空闲了预定的时间段，则该请求由计算机系统断言。 当执行HALT指令时，微处理器产生停止特殊周期。 停止许可确认并停止特殊循环将微处理器置于低功率状态。 由于微处理器处于低功耗模式，所以L2高速缓冲存储器也被置于低功率模式以进一步节能。 L2高速缓存由同步或异步静态随机存取存储器（SRAM）来实现。 要将同步SRAM置于低功耗模式，其地址选通输入置为无效，而芯片选择输入被置为无效。 对于异步SRAM，取消其芯片选择输入将使SRAM转换为低功耗模式。