公开(公告)号：US08174867B2

公开(公告)日：2012-05-08

申请号：US12617437

申请日：2009-11-12

Applicant: Jui-Jen Wu

Inventor： Jui-Jen Wu

IPC: G11C11/00

CPC classification number: G11C11/413 ,  G11C5/145 ,  G11C11/412

Abstract: An integrated circuit structure includes a static random access memory (SRAM) cell; a first power supply node connected to the SRAM cell, wherein the first power supply node is configured to provide a first positive power supply voltage to the SRAM cell; and a bit-line connected to the SRAM cell. A negative-voltage generator is coupled to, and configured to output a negative voltage to, the bit-line, wherein the negative-voltage generator is so configured that the negative voltage decreases in response to a decrease in the first positive power supply voltage and increases in response to an increase in the first positive supply voltage.

Abstract translation: 集成电路结构包括静态随机存取存储器（SRAM）单元; 连接到所述SRAM单元的第一电源节点，其中所述第一电源节点被配置为向所述SRAM单元提供第一正电源电压; 以及连接到SRAM单元的位线。 负电压发生器被耦合到位线并且被配置为向位线输出负电压，其中负电压发生器被配置成使得负电压响应于第一正电源电压的减小而减小，以及 响应于第一正电源电压的增加而增加。

公开(公告)号：US08111542B2

公开(公告)日：2012-02-07

申请号：US12273959

申请日：2008-11-19

Applicant: Jui-Jen Wu ,  Yen-Huei Chen ,  Shao-Yu Chou ,  Hung-Jen Liao

Inventor： Jui-Jen Wu ,  Yen-Huei Chen ,  Shao-Yu Chou ,  Hung-Jen Liao

IPC: G11C11/00

CPC classification number: G11C11/412

Abstract: This invention discloses a static random access memory (SRAM) cell comprising a pair of cross-coupled inverters having a storage node, and a NMOS transistor having a gate terminal, a first and a second source/drain terminal connected to the storage node, a read word-line (RWL) and a read bit-line (RBL), respectively, the RWL and RBL being activated during a read operation and not being activated during any write operation.

Abstract translation: 本发明公开了一种静态随机存取存储器（SRAM）单元，其包括具有存储节点的一对交叉耦合的反相器，以及具有栅极端子，连接到存储节点的第一和第二源极/漏极端子的NMOS晶体管， 分别读取字线（RWL）和读位线（RBL），RWL和RBL在读操作期间被激活，并且在任何写操作期间未被激活。

公开(公告)号：US20110235448A1

公开(公告)日：2011-09-29

申请号：US12732931

申请日：2010-03-26

Applicant: Jui-Jen WU

Inventor： Jui-Jen WU

IPC: G11C7/00 ,  G11C7/06

CPC classification number: G11C7/12 ,  G11C7/08 ,  G11C7/18 ,  G11C8/14 ,  G11C11/413 ,  G11C2207/002 ,  G11C2207/005

Abstract: In some embodiments related to reading data in a memory cell, the data is driven to a local bit line, which drives a local sense amplifier. Depending on the logic level of the data in the memory cell and thus the local bit line, the local sense amplifier transfers the data on the local bit line to a global bit line. A neighbor global bit line is used as a reference for a global sense amplifier to read the differential data on the global bit line and the neighbor global bit line.

Abstract translation: 在与存储器单元中读取数据相关的一些实施例中，数据被驱动到驱动局部读出放大器的局部位线。 根据存储器单元中的数据的逻辑电平以及局部位线，局部读出放大器将局部位线上的数据传送到全局位线。 相邻全局位线用作全局读出放大器的参考，以读取全局位线和邻近全局位线上的差分数据。

公开(公告)号：US20100165749A1

公开(公告)日：2010-07-01

申请号：US12347140

申请日：2008-12-31

Applicant: Jui-Jen Wu ,  Yi-Tzu Chen

Inventor： Jui-Jen Wu ,  Yi-Tzu Chen

IPC: G11C7/00 ,  G11C7/06

CPC classification number: G11C7/18 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/1078 ,  G11C7/1096 ,  G11C11/413

Abstract: A static random access memory (SRAM) circuit includes a pair of complementary global bit-lines, and a pair of complementary local bit-lines. A global read/write circuit is coupled to, and configured to write a small-swing signal to, the pair of global bit-lines in a write operation. The SRAM circuit further includes a first multiplexer and a second multiplexer, each having a first input and a second input. The first input of the first multiplexer and the first input of the second multiplexer are coupled to different one of the pair of global bit-lines. A sense amplifier includes a first input coupled to an output of the first multiplexer, and a second input coupled to an output of the second multiplexer. The sense amplifier is configured to amplify the small-swing signal to a full-swing signal, and outputs the full-swing signal to the pair of local bit-lines in the write operation.

Abstract translation: 静态随机存取存储器（SRAM）电路包括一对互补的全局位线和一对互补局部位线。 在写入操作中，全局读/写电路耦合到并配置成将小摆动信号写入该对全局位线。 SRAM电路还包括第一多路复用器和第二多路复用器，每个具有第一输入和第二输入。 第一多路复用器的第一输入和第二多路复用器的第一输入耦合到该对全局位线中的不同的一个。 读出放大器包括耦合到第一多路复用器的输出的第一输入和耦合到第二多路复用器的输出的第二输入。 读出放大器被配置为将小摆动信号放大到全摆幅信号，并且在写入操作中将全摆幅信号输出到一对局部位线。

公开(公告)号：US20100165707A1

公开(公告)日：2010-07-01

申请号：US12345125

申请日：2008-12-29

Applicant: Yen-Huei Chen ,  Jui-Jen Wu

Inventor： Yen-Huei Chen ,  Jui-Jen Wu

IPC: G11C11/00 ,  G11C7/00

CPC classification number: G11C11/412 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/7855

Abstract: An integrated circuit structure includes a static random access memory (SRAM) cell. The SRAM cell includes a pull-up transistor and a pull-down transistor forming an inverter with the pull-up transistor. The pull-down transistor includes a front gate connected to a gate of the pull-up transistor, and a back-gate decoupled from the front gate.

Abstract translation: 集成电路结构包括静态随机存取存储器（SRAM）单元。 SRAM单元包括上拉晶体管和下拉晶体管，其形成具有上拉晶体管的反相器。 下拉晶体管包括连接到上拉晶体管的栅极的前栅极和从前栅极去耦的后栅极。

公开(公告)号：US07612605B2

公开(公告)日：2009-11-03

申请号：US11705642

申请日：2007-02-12

Applicant: Shao-Yu Chou ,  Yen-Huei Chen ,  Jui-Jen Wu ,  Gary Chan

Inventor： Shao-Yu Chou ,  Yen-Huei Chen ,  Jui-Jen Wu ,  Gary Chan

IPC: G05F1/10 ,  G05F3/02

CPC classification number: H02M3/07 ,  G11C5/147

Abstract: A bootstrap voltage generating circuit includes a bias circuit having a first end coupled to a first power source node having an operation voltage, and a second end coupled to a low voltage reference potential, wherein a voltage at the first end is related to the operation voltage in a non-linear way; a charging capacitor having a first end coupled to the load circuit; a charging path between a second end of the charging capacitor and the first end of the bias circuit, wherein the charging path is responsive to a clock signal; a discharging path between the second end of the charging capacitor and the low voltage reference potential, wherein the discharging path is responsive to the clock signal; and a switch circuit connected to the first end of the charging capacitor for setting a voltage thereon, wherein the switch circuit is responsive to the clock signal.

Abstract translation: 自举电压产生电路包括偏置电路，该偏置电路具有耦合到具有操作电压的第一电源节点的第一端和耦合到低电压参考电位的第二端，其中第一端的电压与操作电压相关 以非线性方式; 充电电容器，其具有耦合到所述负载电路的第一端; 所述充电电容器的第二端和所述偏置电路的所述第一端之间的充电路径，其中所述充电路径响应于时钟信号; 所述充电电容器的第二端和所述低电压参考电位之间的放电路径，其中所述放电路径响应于所述时钟信号; 以及连接到充电电容器的第一端的开关电路，用于在其上设置电压，其中开关电路响应于时钟信号。

公开(公告)号：US07535788B2

公开(公告)日：2009-05-19

申请号：US11636173

申请日：2006-12-08

Applicant: Jui-Jen Wu ,  Kun-Lung Chen ,  Hung-Jen Liao ,  Yung-Lung Lin ,  Chen Yen-Huei ,  Dao-Ping Wang

Inventor： Jui-Jen Wu ,  Kun-Lung Chen ,  Hung-Jen Liao ,  Yung-Lung Lin ,  Chen Yen-Huei ,  Dao-Ping Wang

IPC: G11C5/14

CPC classification number: G11C11/413

Abstract: A writing dynamic power control circuit is disclosed, which comprises a BL and its complementary BLB, at least one memory cell coupled to both the BL and BLB, a first NMOS transistor having a source, a drain and a gate coupled to the BL, the Vss and a first data signal, respectively, a second NMOS transistor having a source, a drain and a gate coupled to the BLB, the Vss and a second data signal, respectively, wherein the second data signal is complementary to the first data signal, a first PMOS transistor having a source, a drain and a gate coupled to a high voltage power supply (CVDD) node, the BLB and the BL, respectively, and a second PMOS transistor having a source, a drain and a gate coupled to the CVDD node, the BL and the BLB, respectively.

Abstract translation: 公开了一种写入动态功率控制电路，其包括BL及其互补BLB，耦合到BL和BLB的至少一个存储单元，具有耦合到BL的源极，漏极和栅极的第一NMOS晶体管， Vss和第一数据信号，分别具有耦合到BLB的源极，漏极和栅极的第二NMOS晶体管，Vss和第二数据信号，其中第二数据信号与第一数据信号互补， 第一PMOS晶体管，具有源极，漏极和栅极，分别耦合到高电压电源（CVDD）节点，BLB和BL，以及第二PMOS晶体管，其具有源极，漏极和栅极耦合到 CVDD节点，BL和BLB。

公开(公告)号：US20080191798A1

公开(公告)日：2008-08-14

申请号：US11705642

申请日：2007-02-12

Applicant: Shao-Yu Chou ,  Yen-Huei Chen ,  Jui-Jen Wu ,  Gary Chan

Inventor： Shao-Yu Chou ,  Yen-Huei Chen ,  Jui-Jen Wu ,  Gary Chan

IPC: H02M3/07

CPC classification number: H02M3/07 ,  G11C5/147

Abstract: A bootstrap voltage generating circuit includes a bias circuit having a first end coupled to a first power source node having an operation voltage, and a second end coupled to a low voltage reference potential, wherein a voltage at the first end is related to the operation voltage in a non-linear way; a charging capacitor having a first end coupled to the load circuit; a charging path between a second end of the charging capacitor and the first end of the bias circuit, wherein the charging path is responsive to a clock signal; a discharging path between the second end of the charging capacitor and the low voltage reference potential, wherein the discharging path is responsive to the clock signal; and a switch circuit connected to the first end of the charging capacitor for setting a voltage thereon, wherein the switch circuit is responsive to the clock signal.

Abstract translation: 自举电压产生电路包括偏置电路，该偏置电路具有耦合到具有操作电压的第一电源节点的第一端和耦合到低电压参考电位的第二端，其中第一端的电压与操作电压相关 以非线性方式; 充电电容器，其具有耦合到所述负载电路的第一端; 所述充电电容器的第二端和所述偏置电路的所述第一端之间的充电路径，其中所述充电路径响应于时钟信号; 所述充电电容器的第二端和所述低电压参考电位之间的放电路径，其中所述放电路径响应于所述时钟信号; 以及连接到充电电容器的第一端的开关电路，用于在其上设置电压，其中开关电路响应于时钟信号。

公开(公告)号：US20080144419A1

公开(公告)日：2008-06-19

申请号：US11638187

申请日：2006-12-13

Applicant: Jui-Jen Wu ,  Kun-Lung Chen ,  Hung-Jen Liao ,  Yung-Lung Lin ,  Chen Yen-Huei ,  Dao-Ping Wang

Inventor： Jui-Jen Wu ,  Kun-Lung Chen ,  Hung-Jen Liao ,  Yung-Lung Lin ,  Chen Yen-Huei ,  Dao-Ping Wang

IPC: G11C5/14

CPC classification number: G11C11/412 ,  G11C11/413

Abstract: A power control circuit for an integrated circuit module includes at least one switch device coupled between a supply voltage and a power node of the integrated circuit module; and a switch control module having a first terminal coupled to the switch device, a second terminal coupled to a control signal, a third terminal coupled to a first storage node of at least one tracking cell, a fourth terminal coupled to a second storage node of the tracking cell, and a fifth terminal coupled to the power node of the integrated circuit module, for controlling the switch device to pass the supply voltage to the power node with or without a substantial voltage drop depending on an operation mode of the integrated circuit module.

Abstract translation: 用于集成电路模块的功率控制电路包括耦合在电源电压和集成电路模块的功率节点之间的至少一个开关装置; 以及开关控制模块，其具有耦合到所述开关装置的第一端子，耦合到控制信号的第二端子，耦合到至少一个跟踪单元的第一存储节点的第三端子，耦合到所述至少一个跟踪单元的第二存储节点的第四端子 跟踪单元和耦合到集成电路模块的功率节点的第五端子，用于根据集成电路模块的操作模式控制开关装置将电源电压传递到功率节点，具有或不具有实质的电压降 。

公开(公告)号：US20080013394A1

公开(公告)日：2008-01-17

申请号：US11529882

申请日：2006-09-30

Applicant: Jui-Jen Wu

Inventor： Jui-Jen Wu

IPC: G11C5/14

CPC classification number: G11C5/147 ,  G11C11/417

Abstract: A power control circuit for an integrated circuit module includes at least one switch device coupled between a supply voltage and a node of the integrated circuit module; and a switch control module having a first terminal coupled to the switch device and a second terminal coupled to the node of the integrated circuit module for controlling the switch device to pass the supply voltage to the node with or without a substantial voltage drop depending on an operation mode of the integrated circuit module, the switch control module having at least one capacitor for selectively discharging the node, thereby creating the substantial voltage drop for the supply voltage across the switch device.

Abstract translation: 集成电路模块的功率控制电路包括耦合在电源电压和集成电路模块的节点之间的至少一个开关装置; 以及开关控制模块，其具有耦合到所述开关装置的第一端子和耦合到所述集成电路模块的所述节点的第二端子，用于控制所述开关装置将所述电源电压传递到所述节点，所述电源电压具有或不具有根据 所述开关控制模块具有至少一个用于选择性地对所述节点进行放电的电容器，从而为所述开关器件的电源电压产生实质的电压降。