公开(公告)号：US06333201B1

公开(公告)日：2001-12-25

申请号：US09228552

申请日：1999-01-12

申请人： Ki Young Oh ,  Ki Hyun Yoon

发明人： Ki Young Oh ,  Ki Hyun Yoon

IPC分类号： H01L2100

CPC分类号： H01L28/56

摘要： Method for fabricating a nonvolatile ferroelectric memory, is disclosed, which can prolong a life time of the memory, including the steps of forming an insulating film on a semiconductor substrate, forming a bottom electrode on the insulating film, forming a ferroelectric film on the bottom electrode, wherein the ferroelectric film is formed of a material containing zirconium oxide as a base composition, the material having an antiferroelectric phase which can not be induced to a ferroelectric phase by an electric field, and the induced ferroelectric phase exhibiting a hysteresis in polarization-electric field characteristic and unable to be induced to an antiferroelectric phase by an electric field, and forming a top electrode on the ferroelectric film.

摘要翻译： 公开了一种制造非易失性铁电体存储器的方法，其可以延长存储器的使用寿命，包括在半导体衬底上形成绝缘膜的步骤，在绝缘膜上形成底部电极，在底部形成铁电体膜 电极，其中，所述强电介质膜由含有氧化锆作为基体组成的材料形成，所述材料具有不能通过电场而被诱导到铁电相的反铁电相，并且所述感应铁电相在极化 - 电场特性，并且不能通过电场被引入反铁电相，并且在铁电体膜上形成顶电极。

公开(公告)号：US5854160A

公开(公告)日：1998-12-29

申请号：US872411

申请日：1997-06-10

申请人： Ki Hyun Yoon ,  Woo Sup Kim ,  Jae Beom Kim

发明人： Ki Hyun Yoon ,  Woo Sup Kim ,  Jae Beom Kim

IPC分类号： H01G4/12 ,  C04B35/462 ,  H01Q1/38 ,  C04B35/465

CPC分类号： H01Q1/38 ,  C04B35/462

摘要： A low temperature sintering microwave dielectric composition which can be sintered at a temperature of below 1250.degree. C. The composition includes a composition of xLiO.sub.1/2 --yCaO--.sub.z SmO.sub.3/2 --wTiO.sub.2 --qBO.sub.3/2 where 13.00.ltoreq.x.ltoreq.16.00, 11.00.ltoreq.y.ltoreq.13.00, 18.00.ltoreq.z.ltoreq.21.00, 45.00.ltoreq.w.ltoreq.51.00 and 0

摘要翻译： 可在低于1250℃的温度下烧结的低温烧结微波电介质组合物。该组合物包括xLiO1 / 2-yCaO-zSmO3 / 2-wTiO2-qBO3 / 2的组合物，其中13.00≤x= 16.00，11.00

公开(公告)号：US10074560B2

公开(公告)日：2018-09-11

申请号：US15601045

申请日：2017-05-22

申请人： Ki-hyun Yoon ,  Hauk Han ,  Yeon-sil Sohn ,  Seul-gi Bae ,  Hyun-seok Lim

发明人： Ki-hyun Yoon ,  Hauk Han ,  Yeon-sil Sohn ,  Seul-gi Bae ,  Hyun-seok Lim

IPC分类号： H01L21/768 ,  H01L21/28 ,  H01L29/40 ,  H01L29/66 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11578 ,  H01L29/792 ,  H01L21/822 ,  H01L27/11568 ,  H01L21/8239 ,  H01L27/105 ,  H01L27/11551

CPC分类号： H01L21/76841 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/76843 ,  H01L21/76858 ,  H01L21/76865 ,  H01L21/8221 ,  H01L21/8239 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53271 ,  H01L27/1052 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/401 ,  H01L29/66477 ,  H01L29/78642 ,  H01L29/792 ,  H01L29/7926

摘要： A method of manufacturing a semiconductor device includes forming an insulating pattern layer on a substrate, conformally forming a first conductive layer with a first thickness on the insulating pattern layer, wet etching the first conductive layer to have a second thickness that is less than the first thickness, and forming a second conductive layer on the first conductive layer after wet etching the first conductive layer. The second conductive layer includes a material that is different from a material included in the first conductive layer.

公开(公告)号：US20180090325A1

公开(公告)日：2018-03-29

申请号：US15601045

申请日：2017-05-22

申请人： Ki-hyun YOON ,  Hauk HAN ,  Yeon-sil SOHN ,  Seul-gi BAE ,  Hyun-seok LIM

发明人： Ki-hyun YOON ,  Hauk HAN ,  Yeon-sil SOHN ,  Seul-gi BAE ,  Hyun-seok LIM

IPC分类号： H01L21/28 ,  H01L29/40 ,  H01L29/66 ,  H01L27/11556 ,  H01L27/11582

CPC分类号： H01L21/76841 ,  H01L21/28088 ,  H01L21/8221 ,  H01L21/8239 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53271 ,  H01L27/1052 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/401 ,  H01L29/66477 ,  H01L29/792 ,  H01L29/7926

摘要： A method of manufacturing a semiconductor device includes forming an insulating pattern layer on a substrate, conformally forming a first conductive layer with a first thickness on the insulating pattern layer, wet etching the first conductive layer to have a second thickness that is less than the first thickness, and forming a second conductive layer on the first conductive layer after wet etching the first conductive layer. The second conductive layer includes a material that is different from a material included in the first conductive layer.

公开(公告)号：US20150137259A1

公开(公告)日：2015-05-21

申请号：US14453705

申请日：2014-08-07

申请人： Hauk HAN ,  Yu Min KIM ,  Ki Hyun YOON ,  Myoung Bum LEE ,  Chang Won LEE ,  Joo Yeon HA

发明人： Hauk HAN ,  Yu Min KIM ,  Ki Hyun YOON ,  Myoung Bum LEE ,  Chang Won LEE ,  Joo Yeon HA

IPC分类号： H01L29/417 ,  H01L27/088 ,  H01L29/45

CPC分类号： H01L29/4175 ,  H01L21/76856 ,  H01L21/76879 ,  H01L23/5226 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a substrate including a conductive region, an insulating layer disposed on the substrate and including an opening exposing the conductive region, and a conductive layer buried within the opening and including a first region disposed on inner side walls of the opening and a second region disposed within the first region. The first region includes a plurality of first crystal grains and the second region includes a plurality of second crystal grains. The pluralities of first and second crystal grains are separated from each other at a boundary formed between the first and second regions.

摘要翻译： 一种半导体器件包括：衬底，其包括导电区域，绝缘层设置在衬底上并且包括暴露导电区域的开口;以及导电层，其被埋在开口内，并且包括设置在开口的内侧壁上的第一区域和 第二区域设置在第一区域内。 第一区域包括多个第一晶粒，第二区域包括多个第二晶粒。 多个第一和第二晶粒在第一和第二区域之间形成的边界处彼此分离。

公开(公告)号：USD675380S1

公开(公告)日：2013-01-29

申请号：US29419094

申请日：2012-04-25

申请人： Ki-Hyun Yoon

设计人： Ki-Hyun Yoon

公开(公告)号：USD629159S1

公开(公告)日：2010-12-14

申请号：US29356724

申请日：2010-03-02

申请人： Ki-Hyun Yoon

设计人： Ki-Hyun Yoon

公开(公告)号：USD549675S1

公开(公告)日：2007-08-28

申请号：US29245333

申请日：2005-12-21

申请人： Ki-Hyun Yoon ,  Rod White

设计人： Ki-Hyun Yoon ,  Rod White

公开(公告)号：USD635384S1

公开(公告)日：2011-04-05

申请号：US29356725

申请日：2010-03-02

申请人： Ki-Hyun Yoon

设计人： Ki-Hyun Yoon

公开(公告)号：USD546318S1

公开(公告)日：2007-07-10

申请号：US29245336

申请日：2005-12-21

申请人： Ki-Hyun Yoon ,  Rod White

设计人： Ki-Hyun Yoon ,  Rod White