公开(公告)号：US20090064061A1

公开(公告)日：2009-03-05

申请号：US11846017

申请日：2007-08-28

Applicant: Veit Gernhoefer ,  Michael S. Gray ,  Matthew T. Guzowski ,  Jason D. Hibbeler ,  Stephen L. Runyon ,  Robert F. Walker ,  Bruce C. Wheeler

Inventor： Veit Gernhoefer ,  Michael S. Gray ,  Matthew T. Guzowski ,  Jason D. Hibbeler ,  Stephen L. Runyon ,  Robert F. Walker ,  Bruce C. Wheeler

IPC: G06F17/50

CPC classification number: G06F17/5072

Abstract: A method of layout optimization containing parameterized cells includes reading a physical design containing parameterized cells, creating a new version for each of usage of a given parameterized cell. The method optimizes physical design shapes of each new version of the parameterized cell by assigning variables to parameters of the parameterized cell according to a desired objective. Then, the method updates the parameters of each new version of the parameterized cell and replaces each new version of the parameterized cell with an instance of the parameterized cell having updated parameters. The method can optionally adjust physical design shapes based on constraints related to the parameters.

Abstract translation: 包含参数化单元格的布局优化方法包括读取包含参数化单元格的物理设计，为给定参数化单元格的每个使用创建新版本。 该方法通过根据期望的目标将参数分配给参数化单元的参数来优化每个新版本的参数化单元的物理设计形状。 然后，该方法更新参数化单元的每个新版本的参数，并用具有更新参数的参数化单元的实例替换参数化单元的每个新版本。 该方法可以基于与参数相关的约束来可选地调整物理设计形状。

公开(公告)号：US07490308B2

公开(公告)日：2009-02-10

申请号：US11278162

申请日：2006-03-31

Applicant: Christopher J. Gonzalez ,  Michael S. Gray ,  Matthew T. Guzowski ,  Jason D. Hibbeler ,  Stephen I. Runyon ,  Xiaoyun K. Wu

Inventor： Christopher J. Gonzalez ,  Michael S. Gray ,  Matthew T. Guzowski ,  Jason D. Hibbeler ,  Stephen I. Runyon ,  Xiaoyun K. Wu

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F2217/08

Abstract: A method of modifying a VLSI layout for performance optimization includes defining a revised set of ground rules for a plurality of original device shapes to be modified and flattening the plurality of original device shapes to a prime cell. A layout optimization operation is performed on the flattened device shapes, based on the revised set of ground rules, so as to create a plurality of revised device shapes. An overlay cell is then created from a difference between the revised device shapes and the original device shapes.

Abstract translation: 修改用于性能优化的VLSI布局的方法包括为要修改的多个原始设备形状定义修改的基本规则集，并将多个原始设备形状平坦化为主单元。 基于经修改的基础规则集，对平坦化的设备形状执行布局优化操作，以便创建多个修改的设备形状。 然后从修改的设备形状和原始设备形状之间的差异创建覆盖单元。

公开(公告)号：US08627247B1

公开(公告)日：2014-01-07

申请号：US13546562

申请日：2012-07-11

Applicant: Kevin W. McCullen ,  Matthew T. Guzowski ,  Rani Narayan ,  Xiaoping Tang ,  Xin Yuan

Inventor： Kevin W. McCullen ,  Matthew T. Guzowski ,  Rani Narayan ,  Xiaoping Tang ,  Xin Yuan

IPC: G06F17/50

CPC classification number: G06F17/5072

Abstract: Approaches are provided for fixing pin mismatches from swapping library cells in layout migration. Specifically, a method is provided that includes collecting information about a first technology pin from a library cell in a first technology. The method further includes swapping the library cell in the first technology with a library cell in a second technology. The method further includes collecting information about a second technology pin from the library cell in the second technology. The method further includes building a pin-mapping table that is configured to map the first technology pin to the second technology pin. The method further includes scaling a layout from the first technology to the second technology. The method further includes modifying the layout based on the pin-mapping table to match the at least one first technology pin to the at least one second technology pin while satisfying ground rules of the second technology.

Abstract translation: 提供了用于在布局迁移中固定引脚不匹配的方法来交换库单元。 具体地，提供了一种方法，其包括在第一技术中从库单元收集关于第一技术引脚的信息。 该方法还包括在第二技术中用库单元交换第一技术中的库单元。 该方法还包括在第二技术中从库单元收集关于第二技术引脚的信息。 该方法还包括构建引脚映射表，其被配置为将第一技术引脚映射到第二技术引脚。 该方法还包括将布局从第一技术缩放到第二技术。 该方法还包括基于引脚映射表来修改布局，以在满足第二技术的基本规则的同时将至少一个第一技术引脚与至少一个第二技术引脚匹配。

公开(公告)号：US07895562B2

公开(公告)日：2011-02-22

申请号：US11958606

申请日：2007-12-18

Applicant: Michael S. Gray ,  Matthew T. Guzowski ,  Kevin W. McCullen ,  Xiaoping Tang ,  Robert F. Walker ,  Xin Yuan

Inventor： Michael S. Gray ,  Matthew T. Guzowski ,  Kevin W. McCullen ,  Xiaoping Tang ,  Robert F. Walker ,  Xin Yuan

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F2217/08

Abstract: An adaptive weighting method for layout optimization differentiates different priorities by assigning the weight of a higher priority (pi) to be multiple of the weight of a lower priority (pi−1) where W(pi)=mi % W(pi−1. To avoid numerical imprecision, this method keeps the total cost in the objective function within a trustable range by scaling the initial weights in the objectives, while maintaining relativity, to produce the scaled weights.

Abstract translation: 用于布局优化的自适应加权方法通过将较高优先级（pi）的权重分配为较低优先级（pi-1）的权重的倍数来区分不同的优先级，其中W（pi）= mi％W（pi-1） 为了避免数值不精确，该方法将目标函数中的总成本保持在可信范围内，通过缩放目标中的初始权重，同时维持相对性，以产生缩放权重。

公开(公告)号：US20090037850A1

公开(公告)日：2009-02-05

申请号：US11831990

申请日：2007-08-01

Applicant: Michael S. Gray ,  Matthew T. Guzowski ,  Jason D. Hibbeler ,  Robert F. Walker ,  Xin Yuan

Inventor： Michael S. Gray ,  Matthew T. Guzowski ,  Jason D. Hibbeler ,  Robert F. Walker ,  Xin Yuan

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: A method of polygonal area design rule correction for use in an electronic design automation tool for governing integrated circuit (IC) design layouts using one-dimensional (1-D) optimization, with steps of analyzing IC design layout data to identify violating polygons, partitioning violating polygons into rectangles in a direction of optimization, formulating an area constraint for each violating polygon to formulate a global linear programming (LP) problem that includes each constraint for each violating polygon and solving the global LP problem to obtain a real-valued solution. A next LP problem is created for each area constraint, and solved. The creating a next and solving the next LP problem and solving are repeated until the last “next LP problem” is solved using constraints and objectives representing sums or differences of no more than two optimization variables.

Abstract translation: 一种多边形区域设计规则校正方法，用于电子设计自动化工具，用于使用一维（1-D）优化来管理集成电路（IC）设计布局，并分析IC设计布局数据以识别违反多边形，划分 在优化方向上将多边形侵入矩形，为每个违规多边形制定面积约束以制定全局线性规划（LP）问题，其包括每个违反多边形的每个约束，并解决全局LP问题以获得实值解。 为每个区域约束创建下一个LP问题，并解决。 重复创建下一个LP并解决下一个LP问题和解决问题，直到最后的“下一个LP问题”使用表示不超过两个优化变量的和或差的约束和目标来解决。