公开(公告)号：US06434725B1

公开(公告)日：2002-08-13

申请号：US09603592

申请日：2000-06-26

申请人： Michael Bernhard Sommer ,  Larry Broach ,  Herbert Lammering

发明人： Michael Bernhard Sommer ,  Larry Broach ,  Herbert Lammering

IPC分类号： G06F1750

CPC分类号： H01L22/20

摘要： A method for yield correlation for semiconductor chips, in accordance with the present invention, includes providing test data for a plurality of tests on each of a plurality of semiconductor chips. A global parameter is assigned to each chip as a quality measure based on the test data for that chip. Values for a plurality of parameter classes are determined, and each parameter class represents a parameter measured for each chip tested. A correlation between the values of the parameter classes and the global parameter values for the plurality of chips is then determined. The correlation for each of the parameter classes is compared to identify at least one parameter class, which detracts from chip yield.

摘要翻译： 根据本发明的用于半导体芯片的屈服相关性的方法包括在多个半导体芯片中的每一个上提供用于多个测试的测试数据。 基于该芯片的测试数据，将全局参数分配给每个芯片作为质量测量。 确定多个参数类的值，每个参数类表示为每个测试芯片测量的参数。 然后确定多个芯片的参数类别的值和全局参数值之间的相关性。 比较每个参数类的相关性以识别至少一个参数类，这降低了芯片产量。

公开(公告)号：US06434503B1

公开(公告)日：2002-08-13

申请号：US09476449

申请日：1999-12-30

申请人： Michael Bernhard Sommer

发明人： Michael Bernhard Sommer

IPC分类号： G01M1900

CPC分类号： G01R31/31908 ,  G01R31/318307 ,  G06F2201/865

摘要： A method for providing specific test programs from a production test program for testing semiconductor devices, in accordance with the present invention, includes providing a semiconductor device to be tested by a tester and initiating a production test program. The production test program includes a plurality of program files and test code sequences. The production test program is held at a test which is to be extracted, and register information and settings are extracted from the tester for the test to be extracted. The register information and settings are stored in a storage file, and the storage file is assembled and translated to provide an executable test program for an extracted test for testing the semiconductor device or other semiconductor devices.

摘要翻译： 根据本发明的用于从用于测试半导体器件的生产测试程序提供特定测试程序的方法包括提供要由测试者测试并开始生产测试程序的半导体器件。 生产测试程序包括多个程序文件和测试代码序列。 生产测试程序在要提取的测试中进行，并从测试者中提取注册信息和设置以进行抽取。 寄存器信息和设置存储在存储文件中，并且存储文件被组合和转换以提供用于测试半导体器件或其他半导体器件的提取测试的可执行测试程序。

公开(公告)号：US07961514B2

公开(公告)日：2011-06-14

申请号：US12349694

申请日：2009-01-07

申请人： Michael Bernhard Sommer

发明人： Michael Bernhard Sommer

IPC分类号： G11C16/04

CPC分类号： H01L27/11521 ,  G11C16/0483 ,  G11C16/26 ,  H01L27/11519 ,  H01L27/11568 ,  H01L29/7881 ,  H01L29/792

摘要： A semiconductor device is described. A channel area is arranged in a semiconductor substrate between a first contact area and a second contact area. A first programmable structure includes a first control structure. The first programmable structure is arranged such that a conductivity of a first section of the channel area depends on a voltage applicable to the first control structure of the first programmable structure and on an information value stored in the first programmable structure. A second programmable structure includes a second control structure. The second programmable structure is arranged such that a conductivity of a second section of the channel area depends on a voltage applicable to the second control structure of the second programmable structure and on an information value stored in the second programmable structure. The first section and the second section of the channel area are electrically connected in series between the first contact area and the second contact area.

摘要翻译： 描述半导体器件。 沟道区域布置在第一接触区域和第二接触区域之间的半导体衬底中。 第一可编程结构包括第一控制结构。 第一可编程结构被布置成使得通道区域的第一部分的电导率取决于可应用于第一可编程结构的第一控制结构的电压以及存储在第一可编程结构中的信息值。 第二可编程结构包括第二控制结构。 第二可编程结构被布置成使得通道区域的第二部分的电导率取决于可应用于第二可编程结构的第二控制结构的电压以及存储在第二可编程结构中的信息值。 通道区域的第一部分和第二部分串联地电连接在第一接触区域和第二接触区域之间。

公开(公告)号：US07330047B2

公开(公告)日：2008-02-12

申请号：US11033988

申请日：2005-01-13

申请人： Michael Bernhard Sommer

发明人： Michael Bernhard Sommer

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H03K19/00384

摘要： A receiver circuit arrangement includes a receiver circuit an input for receiving an input signal an output for outputting an output signal and an inverter circuit with switching transistors. The input signal is fed to the receiver circuit. At least one control transistor is connected in series with the switching transistors. A control circuit is connected on the input side to a terminal for a reference voltage and on the output side to the control terminal of the control transistor of the inverter circuit. The control circuit is designed such that the control transistor is driven by the regulating switching circuit in the event of deviations of the reference voltage from a voltage value in a reference operating state with a control voltage that deviates with respect to the reference operating state.

摘要翻译： 接收器电路装置包括：接收器电路，用于接收输入信号用于输出输出信号的输出和具有开关晶体管的反相器电路的输入。 输入信号被馈送到接收器电路。 至少一个控制晶体管与开关晶体管串联连接。 控制电路在输入侧连接到用于参考电压的端子，并且在输出侧连接到逆变器电路的控制晶体管的控制端子。 控制电路被设计成使得控制晶体管在参考电压与基准操作状态下的电压值偏离并且相对于参考运行状态偏离的控制电压的情况下由调节开关电路驱动。

公开(公告)号：US07304899B2

公开(公告)日：2007-12-04

申请号：US11234383

申请日：2005-09-26

申请人： Günter Gerstmeier ,  Michael Bernhard Sommer

发明人： Günter Gerstmeier ,  Michael Bernhard Sommer

IPC分类号： G11C7/00

CPC分类号： G11C7/20 ,  G11C29/40 ,  G11C29/44 ,  G11C29/802 ,  G11C29/812 ,  G11C2029/1208 ,  G11C2029/4402

摘要： An integrated semiconductor memory includes programmable elements, which are arranged in a continuous region on a chip area of the integrated semiconductor memory. Operating parameters, for example, word line addresses of defective word lines are stored in the programmable elements in a compressed data format during the fabrication process of the integrated semiconductor memory. Upon activation of the integrated semiconductor memory, the compressed data are read out by a read-out circuit and fed to a decompression circuit. The decompression circuit generates, from a bit sequence of the compressed data with the aid of a decompression algorithm, a bit sequence of decompressed data which are evaluated by a control circuit. The storage of the operating parameters in the compressed data format and the arrangement of the programmable elements in a compact region significantly reduce the space requirement on the semiconductor chip.

摘要翻译： 集成半导体存储器包括布置在集成半导体存储器的芯片区域上的连续区域中的可编程元件。 在集成半导体存储器的制造过程期间，操作参数例如缺陷字线的字线地址以压缩数据格式存储在可编程元件中。 在激活集成半导体存储器时，通过读出电路读出压缩数据并将其馈送到解压缩电路。 解压缩电路借助于解压缩算法从压缩数据的比特序列生成由控制电路评估的解压缩数据的比特序列。 压缩数据格式中的操作参数的存储和紧凑区域中可编程元件的布置显着地减小了半导体芯片上的空间需求。

公开(公告)号：US07274218B2

公开(公告)日：2007-09-25

申请号：US11135642

申请日：2005-05-24

申请人： Michael Bernhard Sommer

发明人： Michael Bernhard Sommer

IPC分类号： H03K19/094

CPC分类号： H03K19/018521

摘要： An integrated circuit includes a first and a second amplifier circuit (10, 20), which are in each case driven by an input signal (Vin) having a high and a low signal level and a reference signal (Vref) having a constant signal level and, on the output side (D11, D21) generate a first control signal (S1) and a second control signal (S2). The control signals (S1, S2) are generated independently of one another and are used to regulate a first controllable resistor (31) and a second controllable resistor (32) of a third amplifier circuit (30). Depending on the resistance value of the first and second controllable resistors (31, 32) of the third amplifier circuit, an output signal (Vout) that is amplified in comparison with the input signal (Vin) can be generated at an output terminal (A). The integrated circuit can be used as an input amplifier of an integrated semiconductor memory and permits an adaptive behavior of the input amplifier with regard to fluctuations of the average absolute input signal level.

摘要翻译： 集成电路包括第一和第二放大器电路（10,20），它们在每种情况下由具有高和低信号电平的输入信号（Vin）和具有恒定信号电平的参考信号（Vref）驱动 并且在输出侧（D 11，D 21）产生第一控制信号（S 1）和第二控制信号（S 2）。 控制信号（S1，S2）彼此独立地产生，并且用于调节第三放大器电路（30）的第一可控电阻（31）和第二可控电阻（32）。 根据第三放大电路的第一和第二可控电阻（31,32）的电阻值，与输入信号（Vin）相比放大的输出信号（Vout）可以在输出端（A ）。 集成电路可以用作集成半导体存储器的输入放大器，并且允许输入放大器关于平均绝对输入信号电平的波动的自适应行为。

公开(公告)号：US20100172176A1

公开(公告)日：2010-07-08

申请号：US12349694

申请日：2009-01-07

申请人： Michael Bernhard Sommer

发明人： Michael Bernhard Sommer

IPC分类号： G11C16/04 ,  G11C16/06 ,  H01L21/00

CPC分类号： H01L27/11521 ,  G11C16/0483 ,  G11C16/26 ,  H01L27/11519 ,  H01L27/11568 ,  H01L29/7881 ,  H01L29/792

摘要： A semiconductor device is described. A channel area is arranged in a semiconductor substrate between a first contact area and a second contact area. A first programmable structure includes a first control structure. The first programmable structure is arranged such that a conductivity of a first section of the channel area depends on a voltage applicable to the first control structure of the first programmable structure and on an information value stored in the first programmable structure. A second programmable structure includes a second control structure. The second programmable structure is arranged such that a conductivity of a second section of the channel area depends on a voltage applicable to the second control structure of the second programmable structure and on an information value stored in the second programmable structure. The first section and the second section of the channel area are electrically connected in series between the first contact area and the second contact area.

摘要翻译： 描述半导体器件。 沟道区域布置在第一接触区域和第二接触区域之间的半导体衬底中。 第一可编程结构包括第一控制结构。 第一可编程结构被布置成使得通道区域的第一部分的电导率取决于可应用于第一可编程结构的第一控制结构的电压以及存储在第一可编程结构中的信息值。 第二可编程结构包括第二控制结构。 第二可编程结构被布置成使得通道区域的第二部分的电导率取决于可应用于第二可编程结构的第二控制结构的电压以及存储在第二可编程结构中的信息值。 通道区域的第一部分和第二部分串联地电连接在第一接触区域和第二接触区域之间。

公开(公告)号：US07619924B2

公开(公告)日：2009-11-17

申请号：US11846914

申请日：2007-08-29

申请人： Michael Bollu ,  Michael Bernhard Sommer

发明人： Michael Bollu ,  Michael Bernhard Sommer

IPC分类号： G11C7/00

CPC分类号： G11C7/062 ,  G11C7/1051 ,  G11C7/1069 ,  G11C16/26 ,  G11C2207/063

摘要： A device for reading out memory information storable in a memory has an integrator and a comparator. The memory provides, in a hold phase, a leakage current, and in a readout phase, a readout current. The readout current is dependent on the stored memory information. The integrator is adapted to integrate a quantity derived from the leakage current during the hold phase, and to provide a leakage voltage corresponding to an integrated leakage current. The integrator is further adapted to integrate a quantity derived from the readout current during the readout phase, and to provide a readout voltage corresponding to an integrated readout current. The comparator may compare the leakage voltage to the readout voltage and provide, in dependence on the comparison, a readout value corresponding to the memory information.

摘要翻译： 用于读出存储在存储器中的存储器信息的装置具有积分器和比较器。 存储器在保持阶段提供泄漏电流，并且在读出阶段提供读出电流。 读出电流取决于存储的存储器信息。 积分器适于在保持阶段期间积分从泄漏电流导出的量，并提供与集成的泄漏电流相对应的泄漏电压。 积分器进一步适于在读出阶段期间积分从读出电流导出的量，并提供对应于积分读出电流的读出电压。 比较器可以将泄漏电压与读出电压进行比较，并根据比较提供对应于存储器信息的读出值。

公开(公告)号：US07246278B2

公开(公告)日：2007-07-17

申请号：US10949935

申请日：2004-09-24

申请人： Christian Stocken ,  Michael Bernhard Sommer

发明人： Christian Stocken ,  Michael Bernhard Sommer

IPC分类号： G11C29/00

CPC分类号： G11C29/56 ,  G11C2029/0407 ,  G11C2029/5602

摘要： An apparatus (1) for testing a memory module (2) suitable for exchanging electrical signals with a motherboard (10) contains a device (8a–8k) suitable for detecting the operating state of at least one semiconductor chip (26a–26m) of the module, which device comprises a first set of signal lines (8a–8k), a microcontroller (3) with a memory device (32) for storing the operating state, said microcontroller being electrically connected to the signal lines (8a–8k), a clock generator (5) suitable for generating an operating clock, said clock generator being electrically connected to the microcontroller (3), and a signal connection (13) suitable for communicating a signal for controlling access to the memory module (2) between the circuit board arrangement (10) and the microcontroller (3) and for communicating to the microcontroller (3) a signal for initiating a process of detecting the operating state.

摘要翻译： 一种用于测试适合于与主板（10）交换电信号的存储器模块（2）的装置（1），其包含适合于检测至少一个半导体芯片（26a- 26m），该装置包括第一组信号线（8a-8k），具有用于存储操作状态的存储器件（32）的微控制器（3），所述微控制器电连接到信号 线路（8a-8k），适于产生工作时钟的时钟发生器（5），所述时钟发生器电连接到微控制器（3），以及信号连接（13），适于传送用于控制访问的信号 到电路板装置（10）和微控制器（3）之间的存储器模块（2）并且用于与微控制器（3）通信用于启动检测操作状态的过程的信号。

公开(公告)号：US07112496B2

公开(公告)日：2006-09-26

申请号：US10864321

申请日：2004-06-10

申请人： Michael Bernhard Sommer

发明人： Michael Bernhard Sommer

IPC分类号： H01L21/336

CPC分类号： H01L27/10894 ,  H01L27/0207 ,  H01L27/10897

摘要： Method for fabricating a semiconductor memory device having auxiliary transistor structures which are required for lithography and etching processes. A protective structure for reducing leakage currents between gate conductor and doped zone is provided. The protective structure is formed as a region doped oppositely to the doped zone.