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    DEVICE AND METHOD FOR READING OUT MEMORY INFORMATION
    2.
    发明申请
    DEVICE AND METHOD FOR READING OUT MEMORY INFORMATION 有权
    用于读出存储器信息的装置和方法

    公开(公告)号：US20080056024A1

    公开(公告)日：2008-03-06

    申请号：US11846914

    申请日：2007-08-29

    申请人： Michael Bollu ,  Michael Sommer

    发明人： Michael Bollu ,  Michael Sommer

    IPC分类号： G11C7/00

    CPC分类号： G11C7/062 ,  G11C7/1051 ,  G11C7/1069 ,  G11C16/26 ,  G11C2207/063

    摘要： A device for reading out memory information storable in a memory has an integrator and a comparator. The memory provides, in a hold phase, a leakage current, and in a readout phase, a readout current. The readout current is dependent on the stored memory information. The integrator is adapted to integrate a quantity derived from the leakage current during the hold phase, and to provide a leakage voltage corresponding to an integrated leakage current. The integrator is further adapted to integrate a quantity derived from the readout current during the readout phase, and to provide a readout voltage corresponding to an integrated readout current. The comparator may compare the leakage voltage to the readout voltage and provide, in dependence on the comparison, a readout value corresponding to the memory information.

    摘要翻译： 用于读出存储在存储器中的存储器信息的装置具有积分器和比较器。 存储器在保持阶段提供泄漏电流，并且在读出阶段提供读出电流。 读出电流取决于存储的存储器信息。 积分器适于在保持阶段期间积分从泄漏电流导出的量，并提供与集成的泄漏电流相对应的泄漏电压。 积分器进一步适于在读出阶段期间积分从读出电流导出的量，并提供对应于积分读出电流的读出电压。 比较器可以将泄漏电压与读出电压进行比较，并根据比较提供对应于存储器信息的读出值。

    Semiconductor memory having charge trapping memory cells and fabrication method
    3.
    发明申请
    Semiconductor memory having charge trapping memory cells and fabrication method 有权
    具有电荷捕获存储单元的半导体存储器和制造方法

    公开(公告)号：US20050286296A1

    公开(公告)日：2005-12-29

    申请号：US11145541

    申请日：2005-06-03

    申请人： Michael Bollu ,  Armin Kohlhase ,  Christoph Ludwig ,  Herbert Palm ,  Josef Willer

    发明人： Michael Bollu ,  Armin Kohlhase ,  Christoph Ludwig ,  Herbert Palm ,  Josef Willer

    IPC分类号： H01L21/8246 ,  H01L27/115 ,  G11C11/34

    CPC分类号： H01L27/11568 ,  H01L27/115

    摘要： In the case of this semiconductor memory having NROM cells, the channel regions of the memory transistors in each case run transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive cross-connections are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and are connected to the bit lines in each case in next but one sequence.

    摘要翻译： 在具有NROM单元的半导体存储器的情况下，存储晶体管的沟道区域在每种情况下相对于相关字线横向延伸，位线布置在字线的顶侧并且以电绝缘的方式 并且存在导电交叉连接，这些交叉连接被布置在字线之间的间隔中并且以与后者的电绝缘的方式布置，并且在下一个序列中在每种情况下连接到位线。

    Memory cell arrangements
    7.
    发明授权
    Memory cell arrangements 有权
    存储单元布置

    公开(公告)号：US07974114B2

    公开(公告)日：2011-07-05

    申请号：US12431060

    申请日：2009-04-28

    申请人： Thomas Nirschl ,  Michael Bollu ,  Mayk Roehrich

    发明人： Thomas Nirschl ,  Michael Bollu ,  Mayk Roehrich

    IPC分类号： G11C5/02

    CPC分类号： H01L27/11565 ,  G11C5/063 ,  G11C7/18 ,  G11C16/0408 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11519 ,  H01L27/11587

    摘要： In an embodiment, a memory cell arrangement is provided. The memory cell arrangement may include a first memory cell and a second memory cell, a first source/drain line coupled to a first source/drain region of the first memory cell and a second source/drain line coupled to a second source/drain region of the first memory cell, and a third source/drain line coupled to a first source/drain region of the second memory cell and a fourth source/drain line coupled to a second source/drain region of the second memory cell, wherein the third source/drain line is disposed proximate to the second source/drain line, and wherein the third source/drain line is disposed in the same metallization level as the second source/drain line.

    摘要翻译： 在一个实施例中，提供了存储单元布置。 存储单元布置可以包括第一存储单元和第二存储单元，耦合到第一存储单元的第一源极/漏极区域的第一源极/漏极线和耦合到第二源极/漏极区域的第二源极/漏极线 以及耦合到所述第二存储单元的第一源极/漏极区域的第三源极/漏极线以及耦合到所述第二存储器单元的第二源极/漏极区域的第四源极/漏极线，其中所述第三存储器单元的第三源极/ 源极/漏极线设置在第二源极/漏极线附近，并且其中第三源极/漏极线设置在与第二源极/漏极线相同的金属化水平处。

    Data retention monitor
    8.
    发明授权
    Data retention monitor 有权
    数据保留监视器

    公开(公告)号：US07864565B2

    公开(公告)日：2011-01-04

    申请号：US11831448

    申请日：2007-07-31

    申请人： Thomas Nirschl ,  Jan Otterstedt ,  Christian Peters ,  Michael Bollu ,  Wolf Allers ,  Michael Sommer

    发明人： Thomas Nirschl ,  Jan Otterstedt ,  Christian Peters ,  Michael Bollu ,  Wolf Allers ,  Michael Sommer

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C13/0033 ,  G11C16/3431 ,  G11C16/349 ,  G11C29/12005 ,  G11C29/50 ,  G11C29/50016

    摘要： A data retention monitor for a memory cell including a voltage source and a voltage comparator. The voltage source is adapted to provide a selectable voltage to the memory cell. The selectable voltage includes a read voltage and a test voltage, with the test voltage being greater than the read voltage. The voltage comparator is adapted to compare a voltage of the memory cell with a reference voltage after the provision of the selectable voltage to the memory cell. The memory cell retains data when the memory cell voltage generated at least in part by the test voltage is substantially equal to the reference voltage.

    摘要翻译： 一种用于包括电压源和电压比较器的存储单元的数据保持监视器。 电压源适于向存储器单元提供可选择的电压。 可选择的电压包括读取电压和测试电压，测试电压大于读取电压。 电压比较器适于在将存储单元提供可选择的电压之后将存储单元的电压与参考电压进行比较。 当至少部分由测试电压产生的存储单元电压基本上等于参考电压时，存储单元保留数据。

    Device for the jump-like addressing of specific lines of a serially operating digital memory
    9.
    发明授权
    Device for the jump-like addressing of specific lines of a serially operating digital memory 失效
    用于串行操作数字存储器的特定线路的跳转寻址的设备

    公开(公告)号：US6138227A

    公开(公告)日：2000-10-24

    申请号：US43046

    申请日：1998-03-13

    申请人： Roland Thewes ,  Doris Schmitt-Landsiedel ,  Paul-Werner von Basse ,  Michael Bollu

    发明人： Roland Thewes ,  Doris Schmitt-Landsiedel ,  Paul-Werner von Basse ,  Michael Bollu

    IPC分类号： G11C8/04 ,  G06F12/02

    CPC分类号： G11C8/04

    摘要： A digital memory matrix having memory cells in rows and columns, addressing of the memory cells is accomplished by control devices which perform arbitrary jumps of address, thereby avoiding addressing on adjacent lines. The jump increment is selectable. The control devices are control chains, two of which are provided, and the outputs of the control chains are connected to linking elements that in turn are connected to the memory lines. The linking elements are provided in groups.

    摘要翻译： PCT No.PCT / DE96 / 01511 Sec。 371日期1998年3月13日 102（e）1998年3月13日PCT PCT 1996年8月13日PCT公布。 公开号WO97 / 10600 日期1997年3月20日具有行和列的存储单元的数字存储器矩阵，存储器单元的寻址由执行地址的任意跳跃的控制设备实现，从而避免在相邻行上寻址。 跳跃增量可选。 控制装置是控制链，其中两个被提供，并且控制链的输出连接到链接元件，连接元件又连接到存储器线。 连接元件分组提供。