Abstract:
A pixel clock generator includes a frequency divider 4 that generates a pixel clock PCLK based on a high frequency clock VCLK, a comparator 5 that calculates an error Lerr in the time obtained by integrating a cycle of the pixel clock PCLK for a target number RefN from a time when synchronization signals SPSYNC and EPSYNC are detected, a filter 6, and a frequency calculating unit 7 that sets a frequency dividing value M of the frequency divider 4. The filter 6 and the frequency calculating unit 7 calculate an average of a frequency of the pixel clock PCLK based on the error Lerr, determine a reference error value from the error Lerr in N-cycles, calculate offset values of the frequencies of N pieces of pixel clocks PCLK based on a difference between the reference error value and the error Lerr, and calculate the frequency dividing value M based on a result obtained by adding the circularly selected offset values and the average of the frequency of the pixel clock PCLK.
Abstract:
A light source driving unit includes a modulating signal generating section generating modulating signals based on driving waveform generating information of a light source, a current source selecting section selecting one or more currents output from current sources based on the modulating signals, a light source driving section generating a current having multi-levels based on the one or more currents selected and supplying the generated current to the light source to drive the light source so that light in multi-levels is generated from the light source, and a cancelling section adding a signal error amount which cancels differences in amounts of signal delays generated between the modulating signal generating section and the light source driving section at a stage prior to the current source selecting section.
Abstract:
A light source driving unit includes a modulating signal generating section generating modulating signals based on driving waveform generating information of a light source, a current source selecting section selecting one or more currents output from current sources based on the modulating signals, a light source driving section generating a current having multi-levels based on the one or more currents selected and supplying the generated current to the light source to drive the light source so that light in multi-levels is generated from the light source, and a cancelling section adding a signal error amount which cancels differences in amounts of signal delays generated between the modulating signal generating section and the light source driving section at a stage prior to the current source selecting section.
Abstract:
[Problem to be Solved]Accurate recording is achieved by obtaining each optimum pulse width and pulse edge position in a recording method that performs recording according to the rules of recording waveform using different pulse widths and pulse edge positions for individual data length sets with respect to the data length sets having the different relationship between the number of pulses and the data length. [Means for Solving the Problem]The first trial write process obtains an optimum recording power of a test pattern (S1 through S3) even with respect to data having different rules for the recording waveforms corresponding n type data length sets, and the second trial write process using this optimum recording power obtains optimum pulse width or optimum pulse edge position separately for each data length set (S4 through S6). Based on the optimum recording power and optimum recording waveform obtained by these trial write processes, recording operation is performed so as to form all the data lengths with satisfactory accuracy, thereby making it possible to obtain a proper reproduced signal.
Abstract:
A data recovery method includes the steps of: (a) oversampling data that have been transmitted serially in sync with a first clock of frequency f1, using a multiphase clock generated by shifting a phase of a second clock of frequency f2 at a prescribed interval, the second frequency f2 of the multiphase clock being at or below the first frequency f1; (b) extracting f1/f2 bits on average from the oversampled data; and (c) recovering the extracted bits to restore the received data.
Abstract:
An image forming apparatus reduces superimposing misalignment due to skew difference and registration difference and superimposing misalignment of visible image due to periodic position error generated on a plurality of latent image carriers respectively by correcting image information. A controller of the image forming apparatus has a deviation amount storing unit store data of magnification error in the sub-scanning direction e, executes rotation posture determining process that sets writing rotation posture as rotation angle posture at the time of starting writing latent image on photoconductors for Y, M, C, and K respectively, and has an image data correcting unit correct the image information based on the determined writing rotation posture and various error data (including magnification error in the sub-scanning direction e).
Abstract:
A pixel clock generator includes a frequency divider 4 that generates a pixel clock PCLK based on a high frequency clock VCLK, a comparator 5 that calculates an error Lerr in the time obtained by integrating a cycle of the pixel clock PCLK for a target number RefN from a time when synchronization signals SPSYNC and EPSYNC are detected, a filter 6, and a frequency calculating unit 7 that sets a frequency dividing value M of the frequency divider 4. The filter 6 and the frequency calculating unit 7 calculate an average of a frequency of the pixel clock PCLK based on the error Lerr, determine a reference error value from the error Lerr in N-cycles, calculate offset values of the frequencies of N pieces of pixel clocks PCLK based on a difference between the reference error value and the error Lerr, and calculate the frequency dividing value M based on a result obtained by adding the circularly selected offset values and the average of the frequency of the pixel clock PCLK.
Abstract:
A disclosed device for generating a pulse-width modulated signal according to image data and based on a pixel clock signal includes a pixel clock generating unit configured to generate the pixel clock signal and a modulated data generating unit configured to generate the pulse-width modulated signal. The pixel clock generating unit includes a multi-phase clock signal generating unit, a comparing unit, a frequency calculation unit, a counting unit, and a pixel clock signal output unit. The modulated data generating unit includes a data converting unit, an edge time calculation unit, and a pulse-width modulated signal output unit.
Abstract:
A signal processing apparatus is provided with a converter for converting at least one analog light detection signal into a digital light detection signal, and a signal generator for generating at least one servo error signal by subjecting the digital light detection signal to a predetermined operation process. The signal generator has a function of modifying contents of the operation process.
Abstract:
A signal processing apparatus is provided with a converter for converting at least one analog light detection signal into a digital light detection signal, and a signal generator for generating at least one servo error signal by subjecting the digital light detection signal to a predetermined operation process. The signal generator has a function of modifying contents of the operation process.