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11.发明授权Method and structure for multi-core chip product test and selective voltage binning disposition 有权多核芯片产品测试和选择性电压组合配置的方法和结构公开(公告)号：US09557378B2
公开(公告)日：2017-01-31
申请号：US13553986
申请日：2012-07-20
IPC分类号： H01L21/66 , G01R31/02 , G06F19/00 , G01R31/317 , G06F1/32
CPC分类号： G01R31/31718 , G01R31/31725 , G06F1/32
摘要： Operating speeds of integrated circuit devices are tested to establish maximum and minimum frequency at maximum and minimum voltage. The devices are sorted into relatively-slow and relatively-fast devices to classify the devices into different voltage bins. A bin-specific voltage limit is established for each of the voltage bins needed for core performance at system use conditions. The bin-specific voltage limit is compared to core minimum chip-level functionality voltage at system maximum and minimum frequency specifications. The method correlates system design evaluation of design maximum and minimum frequency at design maximum and minimum voltage conditions with evaluation of tested maximum and minimum frequency at tested maximum and minimum voltage conditions. A chip-specific functionality voltage limit is established for the device. Initial system voltage for all devices from a voltage bin is set at a greater of the bin-specific voltage limit and the chip-specific functionality voltage limit consistent with the evaluation conditions.
摘要翻译： 测试集成电路器件的工作速度，以在最大和最小电压下建立最大和最小频率。 将器件分类为相对较慢且相对较快的器件，以将器件分类到不同的电压仓。 对于在系统使用条件下核心性能所需的每个电压箱，建立了一个特定于特定电压限制。 特定于箱体的电压限制与系统最大和最小频率规格下的核心最小芯片级功能电压进行比较。 该方法在设计最大和最小电压条件下将设计最大和最小频率的系统设计评估与测试的最大和最小电压条件下的最大和最小频率进行了评估。 为器件建立芯片专用功能电压限制。 来自电压仓的所有器件的初始系统电压设置在特定于器件的电压限制和芯片专用功能电压限制的更大值与评估条件一致。
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12.发明授权Content addressable memory with concurrent read and search/compare operations at the same memory cell 有权内容可寻址存储器，在同一个存储单元中具有并发读取和搜索/比较操作公开(公告)号：US08233302B2
公开(公告)日：2012-07-31
申请号：US12983995
申请日：2011-01-04
IPC分类号： G11C15/04
CPC分类号： G11C15/04
摘要： A content addressable memory (CAM) device includes an array of memory cells arranged in rows and columns; compare circuitry configured to indicate match results of search data presented to each row of the array; and compare circuitry configured to indicate match results of search data presented to each column of the array, thereby resulting in a two-dimensional search capability of the array.
摘要翻译： 内容可寻址存储器（CAM）设备包括以行和列布置的存储器单元阵列; 比较电路，被配置为指示呈现给阵列的每一行的搜索数据的匹配结果; 并且比较被配置为指示呈现给阵列的每列的搜索数据的匹配结果的电路，由此导致阵列的二维搜索能力。
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公开(公告)号：US07619923B2
公开(公告)日：2009-11-17
申请号：US11950459
申请日：2007-12-05
IPC分类号： G11C11/34
CPC分类号： G11C7/12 , G11C7/1051 , G11C7/1069 , G11C7/18
摘要： A circuit for reducing current leakage in hierarchical bit-line architectures includes a sense amplifier having transistors, the sense amplifier coupled to bit-lines of cells in a memory array, the sense amplifier configured for detecting stored data from one of the cells; an output latch having transistors, the output latch selectively coupled to a global bit-line of the sense amplifier having a logical state, the output latch configured for selectively reading out stored data from one of the cells through the global bit-line; and a transmission gating device coupled between the sense amplifier and the output latch for selectively coupling the sense amplifier to the output latch correspondingly eliminating a first leakage path and forming a second leakage path, the first leakage path being between the sense amplifier and the output latch, the second leakage path formed within the sense amplifier.
摘要翻译： 用于降低分级位线架构中的电流泄漏的电路包括具有晶体管的读出放大器，读出放大器耦合到存储器阵列中的单元的位线，该读出放大器配置用于检测来自其中一个单元的存储数据; 具有晶体管的输出锁存器，所述输出锁存器选择性地耦合到具有逻辑状态的所述读出放大器的全局位线，所述输出锁存器被配置为经由所述全局位线选择性地从所述单元之一读出存储的数据; 以及耦合在所述读出放大器和所述输出锁存器之间的传输选通装置，用于选择性地将所述读出放大器耦合到所述输出锁存器，以相应地消除第一泄漏路径并形成第二泄漏路径，所述第一泄漏路径位于所述读出放大器和所述输出锁存器 ，形成在读出放大器内的第二泄漏路径。
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公开(公告)号：US07515449B2
公开(公告)日：2009-04-07
申请号：US11532233
申请日：2006-09-15
IPC分类号： G11C15/00
摘要： This patent describes a method for switching search-lines in a Content Addressable Memory (CAM) asynchronously to improve CAM speed and reduce CAM noise without affecting its power performance. This is accomplished by resetting the match-lines prior to initiating a search and then applying a search word to the search-lines. A reference match-line is provided to generate the timing for the search operation and provide the timing for the asynchronous application of the search data on the SLs. Additional noise reduction is achieved through the staggering of the search data application on the SLs through programmable delay elements.
摘要翻译： 该专利描述了用于在内容寻址存储器（CAM）中异步地切换搜索线以提高CAM速度并降低CAM噪声而不影响其功率性能的方法。 这是通过在发起搜索之前重置匹配线，然后将搜索词应用于搜索线来实现的。 提供参考匹配线以产生用于搜索操作的定时，并为SL上的搜索数据的异步应用提供定时。 通过可编程延迟元件在SL上搜索数据应用的交错来实现额外的降噪。
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公开(公告)号：US06920525B2
公开(公告)日：2005-07-19
申请号：US10199788
申请日：2002-07-19
申请人： Thomas B. Chadwick , Tarl S. Gordon , Rahul K. Nadkarni , Michael R. Ouellette , Jeremy Rowland
发明人： Thomas B. Chadwick , Tarl S. Gordon , Rahul K. Nadkarni , Michael R. Ouellette , Jeremy Rowland
CPC分类号： G11C29/816 , G11C15/00 , G11C29/848
摘要： A local word-line redundancy architecture and method that implements both word-line and match-line steering for semiconductor memories and more particularly for content-addressable memories (CAM) are introduced. According to the present invention, the method of performing local word-line redundancy comprising: testing by using BIST, storing results, comparing failing read address data and failing match-line address data to determine if redundancy is possible and, if so, storing the redundancy repair data pattern and loading that patten upon initialization so that redundancy steering is activated.
摘要翻译： 介绍了实现半导体存储器的字线和匹配线转向的局部字线冗余架构和方法，特别是用于内容寻址存储器（CAM）的本地字线冗余架构和方法。 根据本发明，执行本地字线冗余的方法包括：通过使用BIST测试，存储结果，比较失败的读地址数据和失败的匹配行地址数据，以确定冗余是否可能，如果是，则存储 冗余修复数据模式和初始化时的装载，从而激活冗余转向。
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