Column Path Circuit
    11.
    发明申请
    Column Path Circuit 有权
    列路径电路

    公开(公告)号:US20090040845A1

    公开(公告)日:2009-02-12

    申请号:US12190281

    申请日:2008-08-12

    Applicant: Sang Kwon Lee

    Inventor: Sang Kwon Lee

    Abstract: A column path circuit includes address transition detectors which detect level transition of page address signals, thereby outputting transition detection signals each having a predetermined enable period, respectively. A detection signal coupler logically operates on the transition detection signals respectively outputted from the address transition detectors, and outputs a signal representing the results of the logical operation. A ready signal generator outputs a strobe ready signal having a predetermined enable period in response to an enabled state of the signal outputted from the detection signal coupler. A strobe signal generator generates a read strobe signal and a page address strobe signal for latch of the page address signals in response to the strobe ready signal. Page address buffers are enabled by the page address strobe signal, and latch the page address signals, thereby buffering the page address signals, a page address decoder which decodes the buffered page address signals respectively outputted from the page address buffers. And, a column selection signal generator outputs column selection signals respectively corresponding to the decoded page address signals in response to the read strobe signal.

    Abstract translation: 列路径电路包括地址转换检测器,其检测寻呼地址信号的电平转换,从而分别输出具有预定使能周期的转移检测信号。 检测信号耦合器对从地址转换检测器分别输出的转移检测信号进行逻辑运算,并输出表示逻辑运算结果的信号。 就绪信号发生器响应于从检测信号耦合器输出的信号的使能状态而输出具有预定使能周期的选通准备信号。 选通信号发生器响应于选通准备就绪信号而产生读选通信号和页寻址选通信号,用于锁存页地址信号。 页面地址选通信号使能页面地址缓冲器,并锁存页面地址信号,从而缓冲页面地址信号,对从页面地址缓冲器分别输出的缓冲页面地址信号进行解码的页面地址解码器。 并且,列选择信号发生器响应于读选通信号输出分别对应于解码页地址信号的列选择信号。

    System and method of sharing contents using messenger
    13.
    发明申请
    System and method of sharing contents using messenger 审中-公开
    使用信使共享内容的系统和方法

    公开(公告)号:US20080098076A1

    公开(公告)日:2008-04-24

    申请号:US11783452

    申请日:2007-04-10

    CPC classification number: H04L51/04 H04L51/10

    Abstract: The present invention provides to a system and method of sharing contents using a messenger program, The system includes a device server which registers Consumer electronic (CE) devices of the same user and CE devices of different users, and generates a messenger account; a messenger server which registers the generated messenger account; and a buddy setting module which sets a buddy relationship among the CE devices of the same user and a buddy relationship among the CE devices of different users, such that contents are shared by the CE devices having the buddy relationship.

    Abstract translation: 本发明提供一种使用信使程序共享内容的系统和方法。该系统包括登记同一用户的消费电子(CE)装置和不同用户的CE装置的装置服务器,并生成信使账号; 登记生成的信使帐号的信使服务器; 以及在不同用户的CE设备之间设置同一用户的CE设备之间的伙伴关系和好友关系的好友设置模块,使得内容由具有伙伴关系的CE设备共享。

    Semiconductor memory apparatus having column decoder for low power consumption
    14.
    发明申请
    Semiconductor memory apparatus having column decoder for low power consumption 有权
    具有低功耗的列解码器的半导体存储装置

    公开(公告)号:US20080080293A1

    公开(公告)日:2008-04-03

    申请号:US11716635

    申请日:2007-03-12

    Applicant: Sang-Kwon Lee

    Inventor: Sang-Kwon Lee

    CPC classification number: G11C8/10 G11C11/4074 G11C11/4087 G11C2207/2227

    Abstract: The present invention relates to a column decoder for low power consumption in a semiconductor memory apparatus. The semiconductor device according to the present invention includes a column select signal decoder, which has a driving voltage input node and uses a driving voltage, for producing a plurality of column select signals by decoding a column select control signal; and a driving voltage supply controller for controlling a supply of the driving voltage to the driving voltage input node.

    Abstract translation: 本发明涉及在半导体存储装置中低功耗的列解码器。 根据本发明的半导体器件包括具有驱动电压输入节点并使用驱动电压的列选择信号解码器,用于通过对列选择控制信号进行解码来产生多个列选择信号; 以及用于控制对驱动电压输入节点的驱动电压的供给的驱动电压供给控制器。

    Method and apparatus for sharing content assets using picture transfer protocol
    15.
    发明申请
    Method and apparatus for sharing content assets using picture transfer protocol 审中-公开
    使用图片传输协议共享内容资产的方法和装置

    公开(公告)号:US20080010255A1

    公开(公告)日:2008-01-10

    申请号:US11635484

    申请日:2006-12-08

    Abstract: Provided is a method and apparatus for sharing content assets using a picture transfer protocol (PTP). The method, in which a first device shares a content asset of a second device, includes requesting for a content asset control file by transmitting an object identifier for the content asset to the second device; and receiving the content asset control file from the second device. Furthermore, in a method of providing a content asset included in a second device to a first device, the method includes receiving a request for a content asset control file from the first device; modifying the content asset control file by additionally recording object identifiers for respective object files included in the content asset to the content asset control file; and transmitting the modified content asset control file to the first device.

    Abstract translation: 提供了一种使用图像传输协议(PTP)共享内容资产的方法和装置。 其中第一设备共享第二设备的内容资产的方法包括通过向第二设备发送用于内容资产的对象标识符来请求内容资产控制文件; 以及从所述第二设备接收所述内容资产控制文件。 此外,在向第一设备提供包括在第二设备中的内容资产的方法中,所述方法包括从所述第一设备接收对内容资产控制文件的请求; 通过向所述内容资产控制文件附加地记录包含在所述内容资产中的各个目标文件的对象标识符来修改所述内容资产控制文件; 以及将所述修改的内容资产控制文件发送到所述第一设备。

    Circuit and method for detecting synchronous mode in a semiconductor memory apparatus
    16.
    发明申请
    Circuit and method for detecting synchronous mode in a semiconductor memory apparatus 失效
    用于在半导体存储装置中检测同步模式的电路和方法

    公开(公告)号:US20070211558A1

    公开(公告)日:2007-09-13

    申请号:US11641044

    申请日:2006-12-19

    Applicant: Sang Kwon Lee

    Inventor: Sang Kwon Lee

    CPC classification number: G11C7/1045 G11C7/22

    Abstract: A circuit for detecting synchronous mode in a semiconductor memory apparatus includes a control unit that controls the driving of a clock according to whether or not a valid address signal is enabled. A driving unit drives the clock according to the control of the control unit. A latch unit latches the clock driven by the driving unit and outputs a synchronous mode signal.

    Abstract translation: 一种用于在半导体存储装置中检测同步模式的电路包括:控制单元,其根据是否启用有效的地址信号来控制时钟的驱动。 驱动单元根据控制单元的控制驱动时钟。 锁存单元锁存由驱动单元驱动的时钟并输出同步模式信号。

    Address buffer and method for buffering address in semiconductor memory apparatus
    17.
    发明申请
    Address buffer and method for buffering address in semiconductor memory apparatus 有权
    用于在半导体存储装置中缓存地址的地址缓冲器和方法

    公开(公告)号:US20070211555A1

    公开(公告)日:2007-09-13

    申请号:US11641032

    申请日:2006-12-19

    Applicant: Sang Kwon Lee

    Inventor: Sang Kwon Lee

    CPC classification number: G11C8/06 G11C8/18

    Abstract: An address buffer in a semiconductor memory apparatus includes: an address input unit that generates a first latch input address from a buffering enable signal and an input address. A clock synchronizing unit generates a second latch input address from the first latch input address and a clock. A synchronous address latch unit generates a synchronous output address from a command pulse signal and the second latch input address. A synchronous mode detecting unit determines whether a mode is a synchronous mode or not from a valid address signal and the clock to generate a synchronous mode signal. An asynchronous address latch unit generates an asynchronous output address from the synchronous mode signal, an address strobing signal, and the second latch input address.

    Abstract translation: 半导体存储装置中的地址缓冲器包括:地址输入单元,其从缓冲使能信号和输入地址生成第一锁存器输入地址。 时钟同步单元从第一锁存器输入地址和时钟产生第二锁存器输入地址。 同步地址锁存单元根据命令脉冲信号和第二锁存器输入地址产生同步输出地址。 同步模式检测单元从有效地址信号和时钟确定模式是否是同步模式,以产生同步模式信号。 异步地址锁存单元从同步模式信号,地址选通信号和第二锁存器输入地址产生异步输出地址。

    Active cycle control circuit and method for semiconductor memory apparatus
    18.
    发明申请
    Active cycle control circuit and method for semiconductor memory apparatus 有权
    半导体存储装置的主动周期控制电路及方法

    公开(公告)号:US20070189096A1

    公开(公告)日:2007-08-16

    申请号:US11647435

    申请日:2006-12-29

    Applicant: Sang Kwon Lee

    Inventor: Sang Kwon Lee

    CPC classification number: G11C11/406 G11C7/1063 G11C2211/4067

    Abstract: An active cycle control circuit includes a refresh active control signal generation unit that generates a refresh active control signal at the same cycle as a refresh request signal at a timing earlier than the refresh request signal, a refresh standby signal output unit that outputs a refresh standby signal according to a refresh active signal and the refresh request signal, and an active control unit that outputs a row active signal for performing a read cycle according to a read command and outputs the refresh active signal according to the refresh active control signal and the refresh standby signal within the read cycle.

    Abstract translation: 一个主动周期控制电路包括一个刷新主动控制信号产生单元,该刷新主动控制信号产生单元在比刷新请求信号更早的时间以与刷新请求信号相同的周期产生刷新主动控制信号;刷新待机信号输出单元,其输出刷新待机 根据刷新活动信号和刷新请求信号的信号,以及根据读取命令输出用于执行读取周期的行活动信号的有源控制单元,并且根据刷新主动控制信号和刷新输出刷新活动信号 待机信号在读周期内。

    PSRAM for performing write-verify-read function
    19.
    发明授权
    PSRAM for performing write-verify-read function 失效
    PSRAM用于执行写入验证读取功能

    公开(公告)号:US07009898B2

    公开(公告)日:2006-03-07

    申请号:US10876778

    申请日:2004-06-28

    CPC classification number: G11C11/40615 G11C8/10 G11C11/401 G11C29/50016

    Abstract: A PSRAM performs a Write-Verify-Read function at a test mode, thereby easily analyzing defects. The PSRAM comprises a test mode decoder, a refresh control block and a precharge control block. The test mode decoder generates a test mode control signal for performing a WVR function when a test mode starts. The refresh control block selectively performs a refresh operation in response to the test mode control signal. The precharge control block selectively performs a precharge operation in response to the test mode control signal outputted from the test mode decoder. Here, the test mode control signal is activated at the test mode so that the refresh operation and the precharge operation are not performed.

    Abstract translation: PSRAM在测试模式下执行写入验证读取功能,从而轻松分析缺陷。 PSRAM包括测试模式解码器,刷新控制块和预充电控制块。 当测试模式开始时,测试模式解码器产生用于执行WVR功能的测试模式控制信号。 刷新控制块根据测试模式控制信号有选择地执行刷新操作。 预充电控制块响应于从测试模式解码器输出的测试模式控制信号选择性地执行预充电操作。 这里,在测试模式下激活测试模式控制信号,使得不执行刷新操作和预充电操作。

    System and method of sharing contents using messenger
    20.
    发明授权
    System and method of sharing contents using messenger 有权
    使用信使共享内容的系统和方法

    公开(公告)号:US09106448B2

    公开(公告)日:2015-08-11

    申请号:US12482958

    申请日:2009-06-11

    CPC classification number: H04L12/581 H04L51/04 H04L51/10

    Abstract: The present invention provides to a system and method of sharing contents using a messenger program. The system includes a device server which registers Consumer electronic (CE) devices of the same user and CE devices of different users, and generates a messenger account; a messenger server which registers the generated messenger account; and a buddy setting module which sets a buddy relationship among the CE devices of the same user and a buddy relationship among the CE devices of different users, such that contents are shared by the CE devices having the buddy relationship.

    Abstract translation: 本发明提供一种使用信使程序共享内容的系统和方法。 该系统包括登记同一用户的消费电子(CE)设备和不同用户的CE设备的设备服务器,并生成信使账号; 登记生成的信使帐号的信使服务器; 以及在不同用户的CE设备之间设置同一用户的CE设备之间的伙伴关系和好友关系的好友设置模块,使得内容由具有伙伴关系的CE设备共享。

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