公开(公告)号：US07009898B2

公开(公告)日：2006-03-07

申请号：US10876778

申请日：2004-06-28

Applicant: Sang Kwon Lee ,  Tae Woo Kwon

Inventor： Sang Kwon Lee ,  Tae Woo Kwon

IPC: G11C7/00

CPC classification number: G11C11/40615 ,  G11C8/10 ,  G11C11/401 ,  G11C29/50016

Abstract: A PSRAM performs a Write-Verify-Read function at a test mode, thereby easily analyzing defects. The PSRAM comprises a test mode decoder, a refresh control block and a precharge control block. The test mode decoder generates a test mode control signal for performing a WVR function when a test mode starts. The refresh control block selectively performs a refresh operation in response to the test mode control signal. The precharge control block selectively performs a precharge operation in response to the test mode control signal outputted from the test mode decoder. Here, the test mode control signal is activated at the test mode so that the refresh operation and the precharge operation are not performed.

Abstract translation: PSRAM在测试模式下执行写入验证读取功能，从而轻松分析缺陷。 PSRAM包括测试模式解码器，刷新控制块和预充电控制块。 当测试模式开始时，测试模式解码器产生用于执行WVR功能的测试模式控制信号。 刷新控制块根据测试模式控制信号有选择地执行刷新操作。 预充电控制块响应于从测试模式解码器输出的测试模式控制信号选择性地执行预充电操作。 这里，在测试模式下激活测试模式控制信号，使得不执行刷新操作和预充电操作。

公开(公告)号：US20080238501A1

公开(公告)日：2008-10-02

申请号：US12005493

申请日：2007-12-27

Applicant: Tae Woo Kwon

Inventor： Tae Woo Kwon

IPC: H03K17/22 ,  H03L7/00

CPC classification number: H03K17/22 ,  H03K17/223 ,  H03K17/6872 ,  H03K2217/0036

Abstract: An initialization signal generating circuit includes a voltage distributor, a first initialization signal generator, a second initialization signal, and a controller. The voltage distributor outputs a voltage signal in response to an external voltage. The first initialization signal generator outputs a first initialization signal in response to the voltage signal output from the voltage distributor. The second initialization signal generator outputs a second initialization signal in response to the voltage signal output from the voltage distributor. The controller blocks the external voltage supplied to the voltage distributor and the first and second initialization signal generators, in response to the first and second initialization signals.

Abstract translation: 初始化信号发生电路包括电压分配器，第一初始化信号发生器，第二初始化信号和控制器。 电压分配器响应于外部电压输出电压信号。 第一初始化信号发生器响应于从电压分配器输出的电压信号输出第一初始化信号。 第二初始化信号发生器响应于从电压分配器输出的电压信号输出第二初始化信号。 响应于第一和第二初始化信号，控制器阻断提供给电压分配器和第一和第二初始化信号发生器的外部电压。

公开(公告)号：US20070291568A1

公开(公告)日：2007-12-20

申请号：US11647468

申请日：2006-12-29

Applicant: Jong Yeol Yang ,  Tae Woo Kwon

Inventor： Jong Yeol Yang ,  Tae Woo Kwon

IPC: G11C7/00 ,  G11C8/00

CPC classification number: G11C11/406 ,  G11C7/04 ,  G11C11/40626 ,  G11C2211/4061

Abstract: A semiconductor memory integrated circuit for controlling a refresh operation includes: a first period generating unit that generates a first periodic signal having an uniformed period; a second period generating unit that generates a second periodic signal according to a first control signal; a period generation control unit that generates a timing signal for every predetermined period; a frequency dividing unit that divides the frequency of the first periodic signal into at least one frequency-divided periodic signals; and a period selection control unit that controls the operation of the second period generating unit according to the at least one frequency-divided periodic signals and the second periodic signal, determines temperature, and outputs one of the frequency-divided periodic signals corresponding to the determined temperature as a refresh signal.

Abstract translation: 一种用于控制刷新操作的半导体存储器集成电路，包括：产生具有均匀周期的第一周期信号的第一周期生成单元; 第二周期生成单元，其根据第一控制信号生成第二周期信号; 周期产生控制单元，用于每个预定周期产生定时信号; 分频单元，其将所述第一周期信号的频率划分为至少一个分频周期信号; 以及周期选择控制单元，其根据所述至少一个分频周期信号和所述第二周期信号来控制所述第二周期生成单元的操作，确定温度，并且输出与所确定的对应的所述分频周期信号中的一个 温度作为刷新信号。

公开(公告)号：US07057952B1

公开(公告)日：2006-06-06

申请号：US10908566

申请日：2005-05-17

Applicant: Yin Jae Lee ,  Tae Woo Kwon

Inventor： Yin Jae Lee ,  Tae Woo Kwon

IPC: G11C7/00

CPC classification number: G11C11/40615 ,  G11C7/12 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/4094 ,  G11C2207/2227

Abstract: A precharge control circuit of a pseudo SRAM including a precharge set signal generation unit configured to output a precharge set signal, a precharge standby signal generation unit configured to output a precharge standby signal, a precharge signal output unit configured to output a precharge signal in response to the precharge set signal and the precharge standby signal, a first precharge control unit configured to forcedly control the output signal of the precharge standby signal generation unit such that the precharge signal is generated in a period where a chip select signal is disabled, in the case where the chip select signal is disabled long for a first time, and a second precharge control unit configured to forcedly control the output signal of the precharge standby signal generation unit such that the precharge signal is generated in a period where the chip select signal is disabled, in the case where the chip select signal is disabled long for a second time longer than the first time, wherein the precharge signal is generated in response to the operation of the first precharge control unit or the second precharge control unit.

Abstract translation: 一种伪SRAM的预充电控制电路，包括：预充电设定信号生成单元，被配置为输出预充电设定信号;预充电待机信号生成单元，被配置为输出预充电待机信号;预充电信号输出单元，其被配置为响应于输出预充电信号 预充电设定信号和预充电待机信号;第一预充电控制单元，被配置为强制地控制预充电待机信号生成单元的输出信号，使得在芯片选择信号被禁止的时段中产生预充电信号， 芯片选择信号第一次长时间禁止的情况，以及第二预充电控制单元，被配置为强制地控制预充电待机信号生成单元的输出信号，使得在片选信号为 在芯片选择信号长时间长于f的情况下长时间禁用的情况 第一时间，其中响应于第一预充电控制单元或第二预充电控制单元的操作而产生预充电信号。

公开(公告)号：US07696796B2

公开(公告)日：2010-04-13

申请号：US12005493

申请日：2007-12-27

Applicant: Tae Woo Kwon

Inventor： Tae Woo Kwon

IPC: H03L7/00

CPC classification number: H03K17/22 ,  H03K17/223 ,  H03K17/6872 ,  H03K2217/0036

Abstract: An initialization signal generating circuit includes a voltage distributor, a first initialization signal generator, a second initialization signal, and a controller. The voltage distributor outputs a voltage signal in response to an external voltage. The first initialization signal generator outputs a first initialization signal in response to the voltage signal output from the voltage distributor. The second initialization signal generator outputs a second initialization signal in response to the voltage signal output from the voltage distributor. The controller blocks the external voltage supplied to the voltage distributor and the first and second initialization signal generators, in response to the first and second initialization signals.

Abstract translation: 初始化信号发生电路包括电压分配器，第一初始化信号发生器，第二初始化信号和控制器。 电压分配器响应于外部电压输出电压信号。 第一初始化信号发生器响应于从电压分配器输出的电压信号输出第一初始化信号。 第二初始化信号发生器响应于从电压分配器输出的电压信号输出第二初始化信号。 响应于第一和第二初始化信号，控制器阻断提供给电压分配器和第一和第二初始化信号发生器的外部电压。

公开(公告)号：US06771098B2

公开(公告)日：2004-08-03

申请号：US10615236

申请日：2003-07-09

Applicant: Tae Woo Kwon

Inventor： Tae Woo Kwon

IPC: H03B100

CPC classification number: H03K19/01728 ,  H03K19/00361

Abstract: Disclosed is a data output buffer having a preset structure. The data output buffer comprises a plurality of groups, each group having two data output buffers, a preset driver for precharging or discharging any one output of two output buffers in each group, a control circuit for generating a control signal to drive the preset driver when outputs of the two output buffers in each group are same, and a set circuit connected between the outputs of the two data output buffers in each group, for making the outputs of the two data output buffer in each group the same level. Therefore, a data output speed of the data output buffer could be improved and the peak current could be also reduced.

Abstract translation: 公开了具有预设结构的数据输出缓冲器。 数据输出缓冲器包括多个组，每个组具有两个数据输出缓冲器，用于对每组中的两个输出缓冲器的任何一个输出进行预充电或放电的预设驱动器，用于产生控制信号以驱动预设驱动器的控制电路， 每个组中的两个输出缓冲器的输出相同，并且设置电路连接在每组中的两个数据输出缓冲器的输出之间，以使每组中的两个数据输出缓冲器的输出相同。 因此，可以提高数据输出缓冲器的数据输出速度，并且还可以降低峰值电流。

公开(公告)号：US5789282A

公开(公告)日：1998-08-04

申请号：US738745

申请日：1996-10-28

Applicant: Sung Wook Yin ,  Tae Woo Kwon

Inventor： Sung Wook Yin ,  Tae Woo Kwon

IPC: H01L21/336 ,  H01L29/786 ,  H01L21/84

CPC classification number: H01L29/66765 ,  H01L29/78624 ,  H01L29/78669

Abstract: A method for fabricating a thin film transistor, comprising the steps of: forming a gate electrode; forming a doped polysilicon film for source/drain at the side wall of the gate electrode, to insulate the gate electrode; forming a gate insulating film; forming an amorphous polysilicon film over the resulting structure; and forming a source/drain region by diffusing the dopants of the doped polysilicon film into the amorphous silicon film, whereby it is possible to form the source/drain region and drain offset structure of a thin film transistor without formation of a source/drain mask and ion implantation and thus, thereby simplifying the overall procedure.

Abstract translation: 一种制造薄膜晶体管的方法，包括以下步骤：形成栅电极; 在栅电极的侧壁处形成用于源极/漏极的掺杂多晶硅膜，以使栅电极绝缘; 形成栅极绝缘膜; 在所得结构上形成非晶多晶硅膜; 以及通过将掺杂多晶硅膜的掺杂剂扩散到非晶硅膜中而形成源极/漏极区域，从而可以形成薄膜晶体管的源极/漏极区域和漏极偏移结构，而不形成源极/漏极掩模 和离子注入，从而简化了整个过程。

公开(公告)号：US07075853B2

公开(公告)日：2006-07-11

申请号：US10879139

申请日：2004-06-30

Applicant: Duk Ju Jeong ,  Tae Woo Kwon

Inventor： Duk Ju Jeong ,  Tae Woo Kwon

IPC: G11C8/00

CPC classification number: G11C7/22 ,  G11C7/08 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/222 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4096 ,  G11C2207/2227 ,  G11C2207/2281

Abstract: A semiconductor memory device including an internal clock doubler including an internal clock doubler for doubling an external clock signal in a read mode to output a double clock signal in response to a plurality of external control signals, and delaying the external clock signal to output a clock control signal; a sense amplifier control signal generator for receiving the clock control signal and a standby signal of the plurality of external control signals signals which represents an output state of data to generate a plurality of sense amplifier control signals for controlling output of output data of a sense amplifier; a sense amplifier output unit for outputting output data of the sense amplifier in response to the plurality of sense amplifier control signals; and an output buffer unit for outputting output data of the sense amplifier synchronously with respect to the double clock signal in response to the standby signal when data are outputted.

Abstract translation: 一种半导体存储器件，包括内部时钟倍增器，包括用于在读取模式下对外部时钟信号进行加倍的内部时钟倍增器，以响应于多个外部控制信号输出双时钟信号，并延迟外部时钟信号以输出时钟 控制信号; 用于接收时钟控制信号的读出放大器控制信号发生器和表示数据的输出状态的多个外部控制信号信号的待机信号，以产生用于控制读出放大器的输出数据的输出的多个读出放大器控制信号 ; 感测放大器输出单元，用于响应于多个读出放大器控制信号输出读出放大器的输出数据; 以及输出缓冲器单元，用于当输出数据时，响应于备用信号，相对于双时钟信号同步地输出读出放大器的输出数据。