公开(公告)号：US06589847B1

公开(公告)日：2003-07-08

申请号：US09631557

申请日：2000-08-03

Applicant: Daniel Kadosh ,  Scott D. Luning ,  Derick J. Wristers

Inventor： Daniel Kadosh ,  Scott D. Luning ,  Derick J. Wristers

IPC: H01L21336

CPC classification number: H01L29/6659 ,  H01L21/26586 ,  H01L29/1045 ,  H01L29/6656

Abstract: The present invention is directed to a method of forming halo implant regions in a semiconductor device. In one illustrative embodiment, the method comprises forming a gate electrode above a semiconducting substrate, the substrate being doped with a first type of dopant material, and forming halo implant regions in the substrate adjacent the gate electrode by performing at least the following steps: performing a first angled implant process using a dopant material that is of a type opposite to the first type of dopant material and performing a second angled implant using a dopant material that is of the same type as the first type of dopant material. The method concludes with performing at least one additional implantation process to further form source/drain regions for the device.

Abstract translation: 本发明涉及一种在半导体器件中形成卤素注入区的方法。 在一个说明性实施例中，该方法包括在半导体衬底之上形成栅电极，该衬底被掺杂有第一种类型的掺杂剂材料，以及通过至少执行以下步骤在邻近栅极的衬底中形成卤素注入区域：执行 使用与第一类型的掺杂剂材料相反的类型的掺杂剂材料并使用与第一类型的掺杂剂材料具有相同类型的掺杂剂材料来执行第二成角度的注入的第一成角度注入工艺。 该方法的结论是执行至少一个额外的注入工艺以进一步形成器件的源极/漏极区域。

公开(公告)号：US06569606B1

公开(公告)日：2003-05-27

申请号：US09626666

申请日：2000-07-27

Applicant: David Donggang Wu ,  William R. Roche ,  Massud Aminpur ,  Scott D. Luning ,  Karen L. E. Turnqest

Inventor： David Donggang Wu ,  William R. Roche ,  Massud Aminpur ,  Scott D. Luning ,  Karen L. E. Turnqest

IPC: G03C500

CPC classification number: H01L29/66492 ,  G03F7/2002 ,  H01L21/0274 ,  H01L21/26586

Abstract: The present invention is directed to a method of forming halo implants in a semiconductor device. In one illustrative embodiment, the method comprises forming a structure above a semiconducting substrate, forming a layer of photoresist above the structure and the substrate, and positioning the substrate in an exposure tool that has a light source and a focal plane. The method further comprises positioning the surface of the layer of photoresist in an exposure plane that is different from the focal plane of the exposure tool, exposing the photoresist to the light source of the exposure tool while the surface of the photoresist is in the exposure plane, and developing the layer of photoresist to define an opening in the layer of photoresist around the structure on the substrate.

Abstract translation: 本发明涉及一种在半导体器件中形成晕轮植入物的方法。 在一个说明性实施例中，该方法包括在半导体衬底上形成结构，在结构和衬底之上形成光致抗蚀剂层，并将衬底定位在具有光源和焦平面的曝光工具中。 该方法还包括将光致抗蚀剂层的表面定位在与曝光工具的焦平面不同的曝光平面中，将光致抗蚀剂暴露于曝光工具的光源，同时光致抗蚀剂的表面处于曝光平面 并且显影所述光致抗蚀剂层以在所述衬底上的所述结构周围的光致抗蚀剂层中限定开口。

公开(公告)号：US06329257B1

公开(公告)日：2001-12-11

申请号：US08994140

申请日：1997-12-19

Applicant: Scott D. Luning ,  Daniel Sobek ,  Timothy J. Thurgate

Inventor： Scott D. Luning ,  Daniel Sobek ,  Timothy J. Thurgate

IPC: H01L21336

CPC classification number: H01L29/0847 ,  H01L21/26586 ,  H01L21/28273 ,  H01L29/36 ,  H01L29/7883

Abstract: A system and method for controlling a characteristic of at least one memory cell on a semiconductor is disclosed. The at least one memory cell includes a gate stack, a source, and a drain. The semiconductor includes a surface. In one aspect, the method and system include providing the gate stack on the semiconductor and providing the source including a source dopant having a local peak in concentration. The local peak in concentration of the source dopant is located under the gate stack and in proximity to a portion of the surface of the semiconductor. In another aspect the method and system includes a memory cell on a semiconductor. The semiconductor includes a surface. The memory cell includes a gate stack on the semiconductor, a source, and a drain. The gate stack has a first edge and a second edge. The source is located in proximity to the first edge of the gate stack. The drain is located in proximity to the second edge of the gate stack. A first portion of the source is disposed under the gate stack. The source includes a source dopant having a local peak in concentration of the source dopant. The local peak in concentration of the source dopant is located under the gate stack and in proximity to a portion of the surface of the semiconductor.

Abstract translation: 公开了一种用于控制半导体上的至少一个存储单元的特性的系统和方法。 所述至少一个存储单元包括栅极堆叠，源极和漏极。 半导体包括表面。 在一个方面，所述方法和系统包括在半导体上提供栅极堆叠并且提供源，其包括具有局部峰浓度的源掺杂剂。 源掺杂剂的局部峰浓度位于栅极堆叠之下并且靠近半导体表面的一部分。 在另一方面，该方法和系统包括半导体上的存储单元。 半导体包括表面。 存储单元包括半导体上的栅极堆叠，源极和漏极。 栅极堆叠具有第一边缘和第二边缘。 源极位于栅堆叠的第一边缘附近。 漏极位于栅堆叠的第二边缘附近。 源极的第一部分设置在栅极堆叠下方。 该源包括源掺杂剂，其具有源掺杂剂浓度的局部峰。 源掺杂剂的局部峰浓度位于栅极堆叠之下并且靠近半导体表面的一部分。

公开(公告)号：US06168637A

公开(公告)日：2001-01-02

申请号：US08991322

申请日：1997-12-16

Applicant: Mark Randolph ,  Timothy J. Thurgate ,  Scott D. Luning

Inventor： Mark Randolph ,  Timothy J. Thurgate ,  Scott D. Luning

IPC: H01L218247

CPC classification number: H01L27/11521 ,  Y10T29/41

Abstract: A method and system for providing a flash memory cell on a semiconductor is disclosed. In one aspect, the method and system include providing a plurality of gate stacks and providing a drain implant at an angle. The plurality of gate stacks define a plurality of drain areas and a plurality of source areas. The angle is measured from a direction perpendicular to the surface of the semiconductor. The angle allows the plurality of gate stacks to block the drain implant from reaching the plurality of source areas. In another aspect, the method and system include providing a plurality of gate stacks and providing a source implant at an angle. The plurality of gate stacks define a plurality of drain areas and a plurality of source areas. The angle is measured from a direction perpendicular to the surface of the semiconductor. The angle allows the plurality of gate stacks to block the source implant from reaching the plurality of drain areas.

Abstract translation: 公开了一种用于在半导体上提供闪存单元的方法和系统。 在一个方面，该方法和系统包括提供多个栅极堆叠并以一定角度提供漏极注入。 多个栅极堆叠限定多个漏极区域和多个源极区域。 该角度是从垂直于半导体表面的方向测量的。 该角度允许多个栅极堆叠阻挡漏极植入物到达多个源极区域。 在另一方面，该方法和系统包括提供多个栅极叠层并以一定角度提供源植入物。 多个栅极堆叠限定多个漏极区域和多个源极区域。 该角度是从垂直于半导体表面的方向测量的。 该角度允许多个栅极堆叠阻挡源植入物到达多个漏极区域。

公开(公告)号：US6153487A

公开(公告)日：2000-11-28

申请号：US40107

申请日：1998-03-17

Applicant: Scott D. Luning ,  Timothy J. Thurgate ,  Daniel Sobek ,  Nicholas H. Tripsas

Inventor： Scott D. Luning ,  Timothy J. Thurgate ,  Daniel Sobek ,  Nicholas H. Tripsas

IPC: H01L21/265 ,  H01L21/336 ,  H01L21/22 ,  H01L21/38 ,  H01L29/76

CPC classification number: H01L29/66825 ,  H01L21/2652

Abstract: The present invention provides a method and system for the formation of semiconductor devices which reduces band-to-band tunneling current and short-channel effects. The method and system includes implanting first low-dose arsenic into an area in the substrate, thermally diffusing the first low-dose arsenic through a portion of the substrate, implanting a second higher-dose arsenic into the area in the substrate, and diffusing the second higher-dose arsenic into the area in the substrate. Under the present invention, the combination of the first and second arsenic implants has a graded lateral profile which reduces band-to-band tunneling current and short-channel effects. The method also improves the reliability and performance of the semiconductor devices.

Abstract translation: 本发明提供一种用于形成半导体器件的方法和系统，其减少带间隧穿电流和短沟道效应。 该方法和系统包括将第一低剂量砷注入到衬底中的区域中，通过衬底的一部分热扩散第一低剂量砷，将第二较高剂量的砷注入到衬底的区域中， 第二高剂量砷进入底物区域。 在本发明中，第一和第二砷植入物的组合具有梯度横向轮廓，其降低带对隧道电流和短通道效应。 该方法还提高了半导体器件的可靠性和性能。

公开(公告)号：US6127222A

公开(公告)日：2000-10-03

申请号：US991687

申请日：1997-12-16

Applicant: Scott D. Luning ,  Mark Randolph

Inventor： Scott D. Luning ,  Mark Randolph

IPC: H01L21/336

CPC classification number: H01L29/66825

Abstract: A system and method for providing a flash memory cell on a semiconductor substrate are disclosed. The system and method include providing a side implant and providing an implant in at least one of a drain or a source of the flash memory cell.

Abstract translation: 公开了一种用于在半导体衬底上提供闪存单元的系统和方法。 该系统和方法包括提供侧植入物并在闪速存储器单元的漏极或源极中的至少一个中提供植入物。

公开(公告)号：US6005808A

公开(公告)日：1999-12-21

申请号：US993570

申请日：1997-12-18

Applicant: Daniel Sobek ,  Timothy James Thurgate ,  Scott D. Luning ,  Vei-Han Chan ,  Sameer S. Haddad

Inventor： Daniel Sobek ,  Timothy James Thurgate ,  Scott D. Luning ,  Vei-Han Chan ,  Sameer S. Haddad

Abstract: A method and apparatus for reducing band-to-band currents during the erasure of a flash EEPROM memory cell is provided. The apparatus has a back biasing connection on the substrate at which a biasing voltage is applied during erasure of the flash EEPROM memory cell. The method of applying the biasing voltage to the back biasing connection during erasure of the flash EEPROM memory cell reduces band-to-band current between the source region and the substrate during erasure of the flash memory cell. This reduction provides for gate size reduction in flash memory cells without inducing detrimental short channel effects.

公开(公告)号：US09373548B2

公开(公告)日：2016-06-21

申请号：US12199659

申请日：2008-08-27

Applicant: Gen Pei ,  Scott D. Luning ,  Johannes van Meer

Inventor： Gen Pei ,  Scott D. Luning ,  Johannes van Meer

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/78

CPC classification number: H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/092 ,  H01L29/7843

Abstract: A CMOS circuit is provided that includes a PMOS transistor, an NMOS transistor adjacent the PMOS transistor in a channel width direction, a compressive stress liner overlying the PMOS transistor, and a tensile stress liner overlying the NMOS transistor. A portion of the compressive stress liner and a portion of the tensile stress liner are in a stacked configuration, and an overlap region of the compressive stress liner and the tensile stress liner is sufficient to result in an enhanced transverse stress in the compressive stress liner or the tensile stress liner.

Abstract translation: 提供了一种CMOS电路，其包括PMOS晶体管，在沟道宽度方向上与PMOS晶体管相邻的NMOS晶体管，覆盖PMOS晶体管的压应力衬垫以及覆盖NMOS晶体管的拉伸应力衬垫。 压缩应力衬垫的一部分和拉伸应力衬垫的一部分处于堆叠构型，并且压应力衬垫和拉伸应力衬垫的重叠区域足以导致压缩应力衬垫中的增强的横向应力或 拉伸应力衬垫。

公开(公告)号：US07572705B1

公开(公告)日：2009-08-11

申请号：US11231647

申请日：2005-09-21

Applicant: Paul R. Besser ,  Scott D. Luning

Inventor： Paul R. Besser ,  Scott D. Luning

IPC: H01L21/336

CPC classification number: H01L29/66628 ,  H01L29/66772

Abstract: A semiconductor device is disclosed having a conductive gate structure overlying a semiconductor layer having a major surface. An isolation material is recessed within a trench region below the major surface of the semiconductor layer. An epitaxial layer is formed overlying a portion of the major surface and on an active region forming a sidewall of the trench.

Abstract translation: 公开了一种半导体器件，其具有覆盖具有主表面的半导体层的导电栅极结构。 隔离材料凹陷在半导体层的主表面下方的沟槽区域内。 形成外延层，覆盖主表面的一部分和形成沟槽侧壁的有源区。

公开(公告)号：US07442601B2

公开(公告)日：2008-10-28

申请号：US11532753

申请日：2006-09-18

Applicant: Gen Pei ,  Scott D. Luning ,  Johannes van Meer

Inventor： Gen Pei ,  Scott D. Luning ,  Johannes van Meer

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/092 ,  H01L29/7843

Abstract: A stress enhanced CMOS circuit and methods for its fabrication are provided. One fabrication method comprises the steps of forming an NMOS transistor and a PMOS transistor adjacent the NMOS transistor in a channel width direction, the PMOS transistor and the NMOS transistor separated by an isolation region. A compressive stress liner is deposited overlying the transistors and the isolation region and is etched to remove the compressive stress liner from the NMOS transistor and from a portion of the isolation region. A tensile stress liner is deposited overlying the transistors, the isolation region, and the compressive stress liner and is etched to remove a portion of the tensile stress liner overlying a portion of the compressive stress liner and to leave the tensile stress liner overlying the NMOS transistor, the isolation region, and a portion of the compressive stress liner.

Abstract translation: 提供了一种应力增强CMOS电路及其制造方法。 一种制造方法包括以下步骤：在沟道宽度方向上形成与NMOS晶体管相邻的NMOS晶体管和PMOS晶体管，PMOS晶体管和NMOS晶体管由隔离区隔开。 压缩应力衬垫沉积在晶体管和隔离区上，并被蚀刻以从NMOS晶体管和隔离区的一部分去除压应力衬垫。 拉伸应力衬垫沉积在晶体管，隔离区域和压缩应力衬垫上，并被蚀刻以去除覆盖压缩应力衬垫的一部分的拉伸应力衬垫的一部分，并且留下覆盖NMOS晶体管的拉伸应力衬垫 ，隔离区域和压缩应力衬垫的一部分。