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    Method and system for using a spacer to offset implant damage and reduce lateral diffusion in flash memory devices
    2.
    发明授权
    Method and system for using a spacer to offset implant damage and reduce lateral diffusion in flash memory devices 有权
    使用间隔物补偿植入物损伤并减少闪存装置中的横向扩散的方法和系统

    公开(公告)号：US06410956B1

    公开(公告)日：2002-06-25

    申请号：US09478864

    申请日：2000-01-07

    申请人： Vei-Han Chan ,  Scott D. Luning ,  Mark Randolph ,  Nicholas H. Tripsas ,  Daniel Sobek ,  Janet Wang ,  Timothy J. Thurgate ,  Sameer Haddad

    发明人： Vei-Han Chan ,  Scott D. Luning ,  Mark Randolph ,  Nicholas H. Tripsas ,  Daniel Sobek ,  Janet Wang ,  Timothy J. Thurgate ,  Sameer Haddad

    IPC分类号： H01L2976

    CPC分类号： H01L29/66825

    摘要： A system and method for providing a memory cell on a semiconductor is disclosed. In one aspect, the method and system include providing at least one gate stack on the semiconductor, depositing at least one spacer, and providing at least one source implant in the semiconductor. The at least one gate stack has an edge. A portion of the at least one spacer is disposed along the edge of the at least one gate stack. In another aspect, the method and system include providing at least one gate stack on the semiconductor, providing a first junction implant in the semiconductor, depositing at least one spacer, and providing a second junction implant in the semiconductor after the at least one spacer is deposited. The at least one gate stack has an edge. A portion of the at least one spacer is disposed at the edge of the at least one gate stack. In a third aspect, the method and system include providing at least one gate stack on the semiconductor, providing at least one source implant in the semiconductor, depositing at least one spacer after the at least one source implant is provided, and providing at least one drain implant in the semiconductor after the spacer is deposited. The at least one gate has an edge. A portion of the at least one spacer is disposed along the edge of the at least one gate.

    摘要翻译： 公开了一种在半导体上提供存储单元的系统和方法。 在一个方面，所述方法和系统包括在半导体上提供至少一个栅极堆叠，沉积至少一个间隔物，以及在半导体中提供至少一个源极注入。 至少一个栅极堆叠具有边缘。 所述至少一个间隔物的一部分沿着所述至少一个栅极叠层的边缘设置。 在另一方面，该方法和系统包括在半导体上提供至少一个栅极叠层，在半导体中提供第一结注入，沉积至少一个间隔物，以及在至少一个间隔物之后在半导体中提供第二结注入 存放 至少一个栅极堆叠具有边缘。 所述至少一个间隔件的一部分设置在所述至少一个栅极叠层的边缘处。 在第三方面，所述方法和系统包括在半导体上提供至少一个栅极堆叠，在半导体中提供至少一个源极注入，在提供至少一个源极植入之后沉积至少一个间隔物，并且提供至少一个 在间隔物沉积之后在半导体中的漏极注入。 至少一个门具有边缘。 所述至少一个间隔物的一部分沿着所述至少一个栅极的边缘设置。

    Approach for the formation of semiconductor devices which reduces band-to-band tunneling current and short-channel effects
    3.
    发明授权
    Approach for the formation of semiconductor devices which reduces band-to-band tunneling current and short-channel effects 失效
    用于形成减少带对隧道电流和短沟道效应的半导体器件的方法

    公开(公告)号：US6153487A

    公开(公告)日：2000-11-28

    申请号：US40107

    申请日：1998-03-17

    申请人： Scott D. Luning ,  Timothy J. Thurgate ,  Daniel Sobek ,  Nicholas H. Tripsas

    发明人： Scott D. Luning ,  Timothy J. Thurgate ,  Daniel Sobek ,  Nicholas H. Tripsas

    IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/22 ,  H01L21/38 ,  H01L29/76

    CPC分类号： H01L29/66825 ,  H01L21/2652

    摘要： The present invention provides a method and system for the formation of semiconductor devices which reduces band-to-band tunneling current and short-channel effects. The method and system includes implanting first low-dose arsenic into an area in the substrate, thermally diffusing the first low-dose arsenic through a portion of the substrate, implanting a second higher-dose arsenic into the area in the substrate, and diffusing the second higher-dose arsenic into the area in the substrate. Under the present invention, the combination of the first and second arsenic implants has a graded lateral profile which reduces band-to-band tunneling current and short-channel effects. The method also improves the reliability and performance of the semiconductor devices.

    摘要翻译： 本发明提供一种用于形成半导体器件的方法和系统，其减少带间隧穿电流和短沟道效应。 该方法和系统包括将第一低剂量砷注入到衬底中的区域中，通过衬底的一部分热扩散第一低剂量砷，将第二较高剂量的砷注入到衬底的区域中， 第二高剂量砷进入底物区域。 在本发明中，第一和第二砷植入物的组合具有梯度横向轮廓，其降低带对隧道电流和短通道效应。 该方法还提高了半导体器件的可靠性和性能。

    Non-uniform threshold voltage adjustment in flash eproms through gate work function alteration
    4.
    发明授权
    Non-uniform threshold voltage adjustment in flash eproms through gate work function alteration 失效
    通过门功功能改变，闪光eprom中的非均匀阈值电压调整

    公开(公告)号：US5888867A

    公开(公告)日：1999-03-30

    申请号：US23241

    申请日：1998-02-13

    申请人： Janet Wang ,  Scott D. Luning ,  Vei-Han Chan ,  Nicholas H. Tripsas

    发明人： Janet Wang ,  Scott D. Luning ,  Vei-Han Chan ,  Nicholas H. Tripsas

    IPC分类号： H01L21/28 ,  H01L21/3215 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L21/8247

    CPC分类号： H01L29/66825 ,  H01L21/2807 ,  H01L21/28105 ,  H01L21/32155 ,  H01L29/42324 ,  H01L29/4966

    摘要： Aspects for forming a Flash EPROM cell with an adjustable threshold voltage are described. In a method aspect, the method includes forming a substrate structure to establish a foundation for cell formation, and forming a gate structure with a floating gate layer comprising polysilicon-germanium (poly-SiGe) of a non-uniform Ge concentration on the substrate structure. The method further includes forming source and drain regions within the substrate structure, the drain region having a different threshold voltage than the source region. In a further aspect, a Flash EPROM cell with an adjustable threshold voltage includes a substrate structure as a foundation for the cell. The cell further includes a gate structure on the substrate structure, the gate structure comprising a floating gate layer of polysilicon-germanium (poly-SiGe) of non-uniform Ge concentration. Additionally, source and drain regions are included in the substrate structure bordering the gate structure, the drain region having a differing threshold voltage than the source region.

    摘要翻译： 描述了形成具有可调阈值电压的闪存EPROM单元的方面。 在方法方面，该方法包括形成衬底结构以建立细胞形成的基础，以及在衬底结构上形成具有包含不均匀Ge浓度的多晶锗（多晶硅）的浮栅的栅极结构 。 该方法还包括在衬底结构内形成源极和漏极区域，漏极区域具有与源极区域不同的阈值电压。 在另一方面，具有可调阈值电压的闪存EPROM单元包括作为单元的基础的衬底结构。 电池还包括在衬底结构上的栅极结构，栅极结构包括具有不均匀Ge浓度的多晶硅 - 锗（多晶SiGe）的浮栅。 此外，源极和漏极区域包括在与栅极结构接壤的衬底结构中，漏极区域具有与源极区域不同的阈值电压。

    Memory device with a selection element and a control line in a substantially similar layer
    6.
    发明授权
    Memory device with a selection element and a control line in a substantially similar layer 有权
    具有选择元件和控制线的存储器件在基本相似的层中

    公开(公告)号：US07696017B1

    公开(公告)日：2010-04-13

    申请号：US12141180

    申请日：2008-06-18

    申请人： Nicholas H. Tripsas ,  Suzette Paugrle

    发明人： Nicholas H. Tripsas ,  Suzette Paugrle

    IPC分类号： H01L21/82

    CPC分类号： H01L27/1021 ,  H01L27/101

    摘要： The invention facilitates manufacture of semiconductor memory components by reducing the number of layers required to implement a semiconductor memory device. The invention provides for a selection element to be formed in the same layer as one of the control lines (e.g. one of the wordline and bitline). In one embodiment of the invention, a diode is implemented as the selection element within the same layer as one of the control lines. Production of the selection element within the same layer as one of the wordline and bitline reduces problems associated with vertical stacking, increases device yield and reduces related production costs. The invention also provides an efficient method of producing memory devices with the selection element in the same layer as one of the control lines.

    摘要翻译： 本发明有利于通过减少实现半导体存储器件所需的层数来制造半导体存储器组件。 本发明提供了一种选择元件，其形成在与控制线之一（例如字线和位线之一）相同的层中。 在本发明的一个实施例中，二极管被实现为与控制线之一在同一层内的选择元件。 生产作为字线和位线之一的同一层内的选择元件可减少与垂直堆叠相关的问题，提高了设备​​产量并降低了相关生产成本。 本发明还提供了一种生产存储器件的有效方法，其中选择元件与控制线之一在同一层中。

    Methods and systems for memory devices
    7.
    发明申请
    Methods and systems for memory devices 有权
    存储器件的方法和系统

    公开(公告)号：US20080175054A1

    公开(公告)日：2008-07-24

    申请号：US11724774

    申请日：2007-03-16

    申请人： Bryan William Hancock ,  Nicholas H. Tripsas ,  Richard C. Blish

    发明人： Bryan William Hancock ,  Nicholas H. Tripsas ,  Richard C. Blish

    IPC分类号： G11C16/06 ,  G11C11/34 ,  G11C29/00 ,  G11C7/00 ,  G11C16/04

    CPC分类号： G11C16/3404 ,  G11C11/5671 ,  G11C16/3418 ,  G11C16/3422 ,  G11C16/3431 ,  G11C2029/0411

    摘要： One embodiment of the invention relates to a method for refreshing a nonvolatile memory array. In the method, a threshold voltage of a multi-bit memory cell is analyzed to determine if it has drifted outside of a number of allowable voltage windows, wherein each allowable voltage windows corresponds to a different multi-bit value. If the threshold voltage of the cell has drifted outside of the number of allowable voltage states, then the cell is recovered by adjusting at least one voltage boundary of at least one of the number of allowable voltage states.

    摘要翻译： 本发明的一个实施例涉及一种用于刷新非易失性存储器阵列的方法。 在该方法中，分析多位存储单元的阈值电压以确定其是否漂移在许多允许电压窗口之外，其中每个可允许电压窗对应于不同的多位值。 如果电池的阈值电压漂移在容许电压状态数之外，则通过调节至少一个容许电压状态数量的至少一个电压边界来恢复电池。

    Planar polymer memory device
    9.
    发明授权
    Planar polymer memory device 有权
    平面聚合物记忆装置

    公开(公告)号：US06977389B2

    公开(公告)日：2005-12-20

    申请号：US10452877

    申请日：2003-06-02

    申请人： Nicholas H. Tripsas ,  Matthew S. Buynoski ,  Uzodinma Okoroanyanwu ,  Suzette K. Pangrle

    发明人： Nicholas H. Tripsas ,  Matthew S. Buynoski ,  Uzodinma Okoroanyanwu ,  Suzette K. Pangrle

    IPC分类号： G11C11/56 ,  G11C13/02 ,  H01L27/115 ,  H01L27/24 ,  H01L27/28 ,  H01L35/24

    CPC分类号： G11C13/0014 ,  B82Y10/00 ,  G11C11/5664 ,  G11C13/0016 ,  H01L27/28 ,  H01L51/0575

    摘要： The present invention provides a planar polymer memory device that can operate as a non-volatile memory device. A planar polymer memory device can be formed with two or more electrodes and an electrode extension associated with one electrode, wherein a selectively conductive medium and dielectric separate the electrodes. The method for forming a planar polymer memory device comprises at least one of forming a first electrode with an associated plug, forming a second electrode, forming a passive layer over the extension, depositing an organic polymer and patterning the organic polymer. The method affords integration of a planar polymer memory device into a semiconductor fabrication process. A thin film diode (TFD) can further be employed with a planar polymer memory device to facilitate programming. The TFD can be formed between the first electrode and the selectively conductive medium or the second electrode and the selectively conductive medium.

    摘要翻译： 本发明提供一种能够作为非易失性存储器件操作的平面聚合物存储器件。 平面聚合物存储器件可以形成有两个或更多个电极和与一个电极相关联的电极延伸，其中选择性导电的介质和电介质分离电极。 用于形成平面聚合物记忆装置的方法包括以下步骤中的至少一种：形成具有相关塞子的第一电极，形成第二电极，在延伸部分上形成钝化层，沉积有机聚合物和图案化有机聚合物。 该方法将平面聚合物存储器件集成到半导体制造工艺中。 还可以使用薄膜二极管（TFD）与平面聚合物存储器件来促进编程。 可以在第一电极和选择性导电介质或第二电极和选择性导电介质之间形成TFD。

    Method(s) facilitating formation of memory cell(s) and patterned conductive
    10.
    发明授权
    Method(s) facilitating formation of memory cell(s) and patterned conductive 失效
    促进形成记忆体和图案化的导电聚合物膜的方法

    公开(公告)号：US06753247B1

    公开(公告)日：2004-06-22

    申请号：US10285183

    申请日：2002-10-31

    申请人： Uzodinma Okoroanyanwu ,  Suzette K. Pangrle ,  Matthew S. Buynoski ,  Nicholas H. Tripsas ,  Mark S. Chang ,  Ramkumar Subramanian ,  Angela T. Hui

    发明人： Uzodinma Okoroanyanwu ,  Suzette K. Pangrle ,  Matthew S. Buynoski ,  Nicholas H. Tripsas ,  Mark S. Chang ,  Ramkumar Subramanian ,  Angela T. Hui

    IPC分类号： H01L214763

    CPC分类号： G11C13/0014 ,  B82Y10/00 ,  G11C13/0016 ,  H01L27/285

    摘要： A methodology for forming a memory cell is disclosed, wherein an organic polymer layer is formed over a conductive layer and an electrode layer is formed over the organic polymer layer. A first via is etched into the electrode and organic polymer layers, and a dielectric material is applied over the stack to at least fill in the first via. A second via is then etched into the dielectric material so as to expose and make the electrode layer available as a top electrode. A wordline is then formed over the dielectric material such that the top electrode is connected to the wordline by way of the second via. A memory device formed in accordance with the disclosed methodology includes a top electrode formed over an organic polymer layer, a conductive layer under the organic polymer layer, a via defined by a dielectric material and located above the top electrode, and a wordline formed over the dielectric material such that the top electrode is connected to the wordline by way of the via.

    摘要翻译： 公开了一种用于形成存储单元的方法，其中在导电层上形成有机聚合物层，并且在有机聚合物层上形成电极层。 将第一通孔蚀刻到电极和有机聚合物层中，并且将电介质材料施加到堆叠上以至少填充在第一通孔中。 然后将第二通道蚀刻到电介质材料中，以暴露并使电极层可用作顶部电极。 然后在电介质材料上形成字线，使得顶部电极通过第二通孔连接到字线。 根据所公开的方法形成的存储器件包括形成在有机聚合物层上的顶部电极，有机聚合物层下面的导电层，由电介质材料限定并位于顶部电极之上的通孔，以及形成在上部电极上的字线 电介质材料，使得顶部电极通过通孔连接到字线。