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    Biasing method and structure for reducing band-to-band and/or avalanche currents during the erase of flash memory devices
    1.
    发明授权
    Biasing method and structure for reducing band-to-band and/or avalanche currents during the erase of flash memory devices 有权
    在擦除闪速存储器件期间减少带 - 带和/或雪崩电流的偏置方法和结构

    公开(公告)号：US06236596B1

    公开(公告)日：2001-05-22

    申请号：US09461376

    申请日：1999-12-15

    申请人： Daniel Sobek ,  Timothy James Thurgate ,  Scott D. Luning ,  Vei-Han Chan ,  Sameer S. Haddad

    发明人： Daniel Sobek ,  Timothy James Thurgate ,  Scott D. Luning ,  Vei-Han Chan ,  Sameer S. Haddad

    IPC分类号： G11C1134

    CPC分类号： G11C16/14

    摘要： A method and apparatus for reducing band-to-band currents during the erasure of a flash EEPROM memory cell is provided. The apparatus has a back biasing connection on the substrate at which a biasing voltage is applied during erasure of the flash EEPROM memory cell. The method of applying the biasing voltage to the back biasing connection during erasure of the flash EEPROM memory cell reduces band-to-band current between the source region and the substrate during erasure of the flash memory cell. This reduction provides for gate size reduction in flash memory cells without inducing detrimental short channel effects.

    摘要翻译： 提供了一种用于在快速EEPROM存储单元的擦除期间减小带 - 带电流的方法和装置。 该装置在衬底上具有背偏压连接，在擦除EEPROM存储单元期间施加偏置电压。 在闪存EEPROM存储单元擦除期间将偏置电压施加到反向偏置连接的方法在擦除闪速存储单元期间减少源区和衬底之间的带间电流。 这种减少提供了闪存单元的栅极尺寸减小，而不会引起有害的短沟道效应。

    Method and system for using a spacer to offset implant damage and reduce lateral diffusion in flash memory devices
    4.
    发明授权
    Method and system for using a spacer to offset implant damage and reduce lateral diffusion in flash memory devices 有权
    使用间隔物补偿植入物损伤并减少闪存装置中的横向扩散的方法和系统

    公开(公告)号：US06410956B1

    公开(公告)日：2002-06-25

    申请号：US09478864

    申请日：2000-01-07

    申请人： Vei-Han Chan ,  Scott D. Luning ,  Mark Randolph ,  Nicholas H. Tripsas ,  Daniel Sobek ,  Janet Wang ,  Timothy J. Thurgate ,  Sameer Haddad

    发明人： Vei-Han Chan ,  Scott D. Luning ,  Mark Randolph ,  Nicholas H. Tripsas ,  Daniel Sobek ,  Janet Wang ,  Timothy J. Thurgate ,  Sameer Haddad

    IPC分类号： H01L2976

    CPC分类号： H01L29/66825

    摘要： A system and method for providing a memory cell on a semiconductor is disclosed. In one aspect, the method and system include providing at least one gate stack on the semiconductor, depositing at least one spacer, and providing at least one source implant in the semiconductor. The at least one gate stack has an edge. A portion of the at least one spacer is disposed along the edge of the at least one gate stack. In another aspect, the method and system include providing at least one gate stack on the semiconductor, providing a first junction implant in the semiconductor, depositing at least one spacer, and providing a second junction implant in the semiconductor after the at least one spacer is deposited. The at least one gate stack has an edge. A portion of the at least one spacer is disposed at the edge of the at least one gate stack. In a third aspect, the method and system include providing at least one gate stack on the semiconductor, providing at least one source implant in the semiconductor, depositing at least one spacer after the at least one source implant is provided, and providing at least one drain implant in the semiconductor after the spacer is deposited. The at least one gate has an edge. A portion of the at least one spacer is disposed along the edge of the at least one gate.

    摘要翻译： 公开了一种在半导体上提供存储单元的系统和方法。 在一个方面，所述方法和系统包括在半导体上提供至少一个栅极堆叠，沉积至少一个间隔物，以及在半导体中提供至少一个源极注入。 至少一个栅极堆叠具有边缘。 所述至少一个间隔物的一部分沿着所述至少一个栅极叠层的边缘设置。 在另一方面，该方法和系统包括在半导体上提供至少一个栅极叠层，在半导体中提供第一结注入，沉积至少一个间隔物，以及在至少一个间隔物之后在半导体中提供第二结注入 存放 至少一个栅极堆叠具有边缘。 所述至少一个间隔件的一部分设置在所述至少一个栅极叠层的边缘处。 在第三方面，所述方法和系统包括在半导体上提供至少一个栅极堆叠，在半导体中提供至少一个源极注入，在提供至少一个源极植入之后沉积至少一个间隔物，并且提供至少一个 在间隔物沉积之后在半导体中的漏极注入。 至少一个门具有边缘。 所述至少一个间隔物的一部分沿着所述至少一个栅极的边缘设置。

    Non-uniform threshold voltage adjustment in flash eproms through gate work function alteration
    5.
    发明授权
    Non-uniform threshold voltage adjustment in flash eproms through gate work function alteration 失效
    通过门功功能改变，闪光eprom中的非均匀阈值电压调整

    公开(公告)号：US5888867A

    公开(公告)日：1999-03-30

    申请号：US23241

    申请日：1998-02-13

    申请人： Janet Wang ,  Scott D. Luning ,  Vei-Han Chan ,  Nicholas H. Tripsas

    发明人： Janet Wang ,  Scott D. Luning ,  Vei-Han Chan ,  Nicholas H. Tripsas

    IPC分类号： H01L21/28 ,  H01L21/3215 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L21/8247

    CPC分类号： H01L29/66825 ,  H01L21/2807 ,  H01L21/28105 ,  H01L21/32155 ,  H01L29/42324 ,  H01L29/4966

    摘要： Aspects for forming a Flash EPROM cell with an adjustable threshold voltage are described. In a method aspect, the method includes forming a substrate structure to establish a foundation for cell formation, and forming a gate structure with a floating gate layer comprising polysilicon-germanium (poly-SiGe) of a non-uniform Ge concentration on the substrate structure. The method further includes forming source and drain regions within the substrate structure, the drain region having a different threshold voltage than the source region. In a further aspect, a Flash EPROM cell with an adjustable threshold voltage includes a substrate structure as a foundation for the cell. The cell further includes a gate structure on the substrate structure, the gate structure comprising a floating gate layer of polysilicon-germanium (poly-SiGe) of non-uniform Ge concentration. Additionally, source and drain regions are included in the substrate structure bordering the gate structure, the drain region having a differing threshold voltage than the source region.

    摘要翻译： 描述了形成具有可调阈值电压的闪存EPROM单元的方面。 在方法方面，该方法包括形成衬底结构以建立细胞形成的基础，以及在衬底结构上形成具有包含不均匀Ge浓度的多晶锗（多晶硅）的浮栅的栅极结构 。 该方法还包括在衬底结构内形成源极和漏极区域，漏极区域具有与源极区域不同的阈值电压。 在另一方面，具有可调阈值电压的闪存EPROM单元包括作为单元的基础的衬底结构。 电池还包括在衬底结构上的栅极结构，栅极结构包括具有不均匀Ge浓度的多晶硅 - 锗（多晶SiGe）的浮栅。 此外，源极和漏极区域包括在与栅极结构接壤的衬底结构中，漏极区域具有与源极区域不同的阈值电压。

    Method for laterally peaked source doping profiles for better erase control in flash memory devices
    6.
    发明授权
    Method for laterally peaked source doping profiles for better erase control in flash memory devices 失效
    用于横向峰值源掺杂分布的方法，用于在闪速存储器件中更好的擦除控制

    公开(公告)号：US06329257B1

    公开(公告)日：2001-12-11

    申请号：US08994140

    申请日：1997-12-19

    申请人： Scott D. Luning ,  Daniel Sobek ,  Timothy J. Thurgate

    发明人： Scott D. Luning ,  Daniel Sobek ,  Timothy J. Thurgate

    IPC分类号： H01L21336

    CPC分类号： H01L29/0847 ,  H01L21/26586 ,  H01L21/28273 ,  H01L29/36 ,  H01L29/7883

    摘要： A system and method for controlling a characteristic of at least one memory cell on a semiconductor is disclosed. The at least one memory cell includes a gate stack, a source, and a drain. The semiconductor includes a surface. In one aspect, the method and system include providing the gate stack on the semiconductor and providing the source including a source dopant having a local peak in concentration. The local peak in concentration of the source dopant is located under the gate stack and in proximity to a portion of the surface of the semiconductor. In another aspect the method and system includes a memory cell on a semiconductor. The semiconductor includes a surface. The memory cell includes a gate stack on the semiconductor, a source, and a drain. The gate stack has a first edge and a second edge. The source is located in proximity to the first edge of the gate stack. The drain is located in proximity to the second edge of the gate stack. A first portion of the source is disposed under the gate stack. The source includes a source dopant having a local peak in concentration of the source dopant. The local peak in concentration of the source dopant is located under the gate stack and in proximity to a portion of the surface of the semiconductor.

    摘要翻译： 公开了一种用于控制半导体上的至少一个存储单元的特性的系统和方法。 所述至少一个存储单元包括栅极堆叠，源极和漏极。 半导体包括表面。 在一个方面，所述方法和系统包括在半导体上提供栅极堆叠并且提供源，其包括具有局部峰浓度的源掺杂剂。 源掺杂剂的局部峰浓度位于栅极堆叠之下并且靠近半导体表面的一部分。 在另一方面，该方法和系统包括半导体上的存储单元。 半导体包括表面。 存储单元包括半导体上的栅极堆叠，源极和漏极。 栅极堆叠具有第一边缘和第二边缘。 源极位于栅堆叠的第一边缘附近。 漏极位于栅堆叠的第二边缘附近。 源极的第一部分设置在栅极堆叠下方。 该源包括源掺杂剂，其具有源掺杂剂浓度的局部峰。 源掺杂剂的局部峰浓度位于栅极堆叠之下并且靠近半导体表面的一部分。

    Approach for the formation of semiconductor devices which reduces band-to-band tunneling current and short-channel effects
    7.
    发明授权
    Approach for the formation of semiconductor devices which reduces band-to-band tunneling current and short-channel effects 失效
    用于形成减少带对隧道电流和短沟道效应的半导体器件的方法

    公开(公告)号：US6153487A

    公开(公告)日：2000-11-28

    申请号：US40107

    申请日：1998-03-17

    申请人： Scott D. Luning ,  Timothy J. Thurgate ,  Daniel Sobek ,  Nicholas H. Tripsas

    发明人： Scott D. Luning ,  Timothy J. Thurgate ,  Daniel Sobek ,  Nicholas H. Tripsas

    IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/22 ,  H01L21/38 ,  H01L29/76

    CPC分类号： H01L29/66825 ,  H01L21/2652

    摘要： The present invention provides a method and system for the formation of semiconductor devices which reduces band-to-band tunneling current and short-channel effects. The method and system includes implanting first low-dose arsenic into an area in the substrate, thermally diffusing the first low-dose arsenic through a portion of the substrate, implanting a second higher-dose arsenic into the area in the substrate, and diffusing the second higher-dose arsenic into the area in the substrate. Under the present invention, the combination of the first and second arsenic implants has a graded lateral profile which reduces band-to-band tunneling current and short-channel effects. The method also improves the reliability and performance of the semiconductor devices.

    摘要翻译： 本发明提供一种用于形成半导体器件的方法和系统，其减少带间隧穿电流和短沟道效应。 该方法和系统包括将第一低剂量砷注入到衬底中的区域中，通过衬底的一部分热扩散第一低剂量砷，将第二较高剂量的砷注入到衬底的区域中， 第二高剂量砷进入底物区域。 在本发明中，第一和第二砷植入物的组合具有梯度横向轮廓，其降低带对隧道电流和短通道效应。 该方法还提高了半导体器件的可靠性和性能。

    Semiconductor device and method of manufacturing a semiconductor device
    8.
    发明授权
    Semiconductor device and method of manufacturing a semiconductor device 有权
    半导体装置及其制造方法

    公开(公告)号：US07910996B2

    公开(公告)日：2011-03-22

    申请号：US12496133

    申请日：2009-07-01

    申请人： Paul R. Besser ,  Scott D. Luning

    发明人： Paul R. Besser ,  Scott D. Luning

    IPC分类号： H01L29/12

    CPC分类号： H01L29/66628 ,  H01L29/66772

    摘要： A semiconductor device is disclosed having a conductive gate structure overlying a semiconductor layer having a major surface. An isolation material is recessed within a trench region below the major surface of the semiconductor layer. An epitaxial layer is formed overlying a portion of the major surface and on an active region forming a sidewall of the trench.

    摘要翻译： 公开了一种半导体器件，其具有覆盖具有主表面的半导体层的导电栅极结构。 隔离材料凹陷在半导体层的主表面下方的沟槽区域内。 形成外延层，覆盖主表面的一部分和形成沟槽侧壁的有源区。

    INTEGRATION SCHEME FOR CONSTRAINED SEG GROWTH ON POLY DURING RAISED S/D PROCESSING
    9.
    发明申请
    INTEGRATION SCHEME FOR CONSTRAINED SEG GROWTH ON POLY DURING RAISED S/D PROCESSING 审中-公开
    在加速S / D处理期间聚合的SEG增长的集成方案

    公开(公告)号：US20090236664A1

    公开(公告)日：2009-09-24

    申请号：US12471600

    申请日：2009-05-26

    申请人： David E. Brown ,  Scott D. Luning

    发明人： David E. Brown ,  Scott D. Luning

    IPC分类号： H01L29/786

    CPC分类号： H01L29/66545 ,  H01L21/0206 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7833

    摘要： A method for constraining lateral growth of gate caps formed during an epitaxial silicon growth process to achieve raised source/drain regions on poly silicon is presented. The method is appropriate for integration into a manufacturing process for integrated circuit semiconductor devices. The method utilizes selective etch processes, dependant upon the material comprising the protective layer (hard mask) over the gate and the material of the spacers, e.g., oxide mask/nitride spacers, or nitride mask/oxide spacers.

    摘要翻译： 提出了一种限制在外延硅生长过程中形成的栅极盖的横向生长以在多晶硅上实现凸起的源极/漏极区域的方法。 该方法适用于集成到集成电路半导体器件的制造工艺中。 该方法利用选择性蚀刻工艺，取决于包含栅极上的保护层（硬掩模）的材料和间隔物的材料，例如氧化物掩模/氮化物间隔物或氮化物掩模/氧化物间隔物。

    Integration scheme for constrained SEG growth on poly during raised S/D processing
    10.
    发明授权
    Integration scheme for constrained SEG growth on poly during raised S/D processing 有权
    在提升的S / D处理期间，聚合物对SEG增长的集成方案

    公开(公告)号：US07553732B1

    公开(公告)日：2009-06-30

    申请号：US11150923

    申请日：2005-06-13

    申请人： David E. Brown ,  Scott D. Luning

    发明人： David E. Brown ,  Scott D. Luning

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66545 ,  H01L21/0206 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7833

    摘要： A method for constraining lateral growth of gate caps formed during an epitaxial silicon growth process to achieve raised source/drain regions on poly silicon is presented. The method is appropriate for integration into a manufacturing process for integrated circuit semiconductor devices. The method utilizes selective etch processes, dependant upon the material comprising the protective layer (hard mask) over the gate and the material of the spacers, e.g., oxide mask/nitride spacers, or nitride mask/oxide spacers.

    摘要翻译： 提出了一种限制在外延硅生长过程中形成的栅极盖的横向生长以在多晶硅上实现凸起的源极/漏极区域的方法。 该方法适用于集成到集成电路半导体器件的制造工艺中。 该方法利用选择性蚀刻工艺，取决于包含栅极上的保护层（硬掩模）的材料和间隔物的材料，例如氧化物掩模/氮化物间隔物或氮化物掩模/氧化物间隔物。