公开(公告)号：US6025240A

公开(公告)日：2000-02-15

申请号：US993600

申请日：1997-12-18

Applicant: Vei-Han Chan ,  Scott D. Luning ,  Mark Randolph ,  Nicholas H. Tripsas ,  Daniel Sobek ,  Janet Wang ,  Timothy J. Thurgate ,  Sameer Haddad

Inventor： Vei-Han Chan ,  Scott D. Luning ,  Mark Randolph ,  Nicholas H. Tripsas ,  Daniel Sobek ,  Janet Wang ,  Timothy J. Thurgate ,  Sameer Haddad

IPC: H01L21/336 ,  H01L21/8247

CPC classification number: H01L29/66825

Abstract: A system and method for providing a memory cell on a semiconductor is disclosed. In one aspect, the method and system include providing at least one gate stack on the semiconductor, depositing at least one spacer, and providing at least one source implant in the semiconductor. The at least one gate stack has an edge. A portion of the at least one spacer is disposed along the edge of the at least one gate stack. In another aspect, the method and system include providing at least one gate stack on the semiconductor, providing a first junction implant in the semiconductor, depositing at least one spacer, and providing a second junction implant in the semiconductor after the at least one spacer is deposited. The at least one gate stack has an edge. A portion of the at least one spacer is disposed at the edge of the at least one gate stack. In a third aspect, the method and system include providing at least one gate stack on the semiconductor, providing at least one source implant in the semiconductor, depositing at least one spacer after the at least one source implant is provided, and providing at least one drain implant in the semiconductor after the spacer is deposited. The at least one gate has an edge. A portion of the at least one spacer is disposed along the edge of the at least one gate.

公开(公告)号：US06410956B1

公开(公告)日：2002-06-25

申请号：US09478864

申请日：2000-01-07

Applicant: Vei-Han Chan ,  Scott D. Luning ,  Mark Randolph ,  Nicholas H. Tripsas ,  Daniel Sobek ,  Janet Wang ,  Timothy J. Thurgate ,  Sameer Haddad

Inventor： Vei-Han Chan ,  Scott D. Luning ,  Mark Randolph ,  Nicholas H. Tripsas ,  Daniel Sobek ,  Janet Wang ,  Timothy J. Thurgate ,  Sameer Haddad

IPC: H01L2976

CPC classification number: H01L29/66825

Abstract: A system and method for providing a memory cell on a semiconductor is disclosed. In one aspect, the method and system include providing at least one gate stack on the semiconductor, depositing at least one spacer, and providing at least one source implant in the semiconductor. The at least one gate stack has an edge. A portion of the at least one spacer is disposed along the edge of the at least one gate stack. In another aspect, the method and system include providing at least one gate stack on the semiconductor, providing a first junction implant in the semiconductor, depositing at least one spacer, and providing a second junction implant in the semiconductor after the at least one spacer is deposited. The at least one gate stack has an edge. A portion of the at least one spacer is disposed at the edge of the at least one gate stack. In a third aspect, the method and system include providing at least one gate stack on the semiconductor, providing at least one source implant in the semiconductor, depositing at least one spacer after the at least one source implant is provided, and providing at least one drain implant in the semiconductor after the spacer is deposited. The at least one gate has an edge. A portion of the at least one spacer is disposed along the edge of the at least one gate.

Abstract translation: 公开了一种在半导体上提供存储单元的系统和方法。 在一个方面，所述方法和系统包括在半导体上提供至少一个栅极堆叠，沉积至少一个间隔物，以及在半导体中提供至少一个源极注入。 至少一个栅极堆叠具有边缘。 所述至少一个间隔物的一部分沿着所述至少一个栅极叠层的边缘设置。 在另一方面，该方法和系统包括在半导体上提供至少一个栅极叠层，在半导体中提供第一结注入，沉积至少一个间隔物，以及在至少一个间隔物之后在半导体中提供第二结注入 存放 至少一个栅极堆叠具有边缘。 所述至少一个间隔件的一部分设置在所述至少一个栅极叠层的边缘处。 在第三方面，所述方法和系统包括在半导体上提供至少一个栅极堆叠，在半导体中提供至少一个源极注入，在提供至少一个源极植入之后沉积至少一个间隔物，并且提供至少一个 在间隔物沉积之后在半导体中的漏极注入。 至少一个门具有边缘。 所述至少一个间隔物的一部分沿着所述至少一个栅极的边缘设置。

公开(公告)号：US06168637A

公开(公告)日：2001-01-02

申请号：US08991322

申请日：1997-12-16

Applicant: Mark Randolph ,  Timothy J. Thurgate ,  Scott D. Luning

Inventor： Mark Randolph ,  Timothy J. Thurgate ,  Scott D. Luning

IPC: H01L218247

CPC classification number: H01L27/11521 ,  Y10T29/41

Abstract: A method and system for providing a flash memory cell on a semiconductor is disclosed. In one aspect, the method and system include providing a plurality of gate stacks and providing a drain implant at an angle. The plurality of gate stacks define a plurality of drain areas and a plurality of source areas. The angle is measured from a direction perpendicular to the surface of the semiconductor. The angle allows the plurality of gate stacks to block the drain implant from reaching the plurality of source areas. In another aspect, the method and system include providing a plurality of gate stacks and providing a source implant at an angle. The plurality of gate stacks define a plurality of drain areas and a plurality of source areas. The angle is measured from a direction perpendicular to the surface of the semiconductor. The angle allows the plurality of gate stacks to block the source implant from reaching the plurality of drain areas.

Abstract translation: 公开了一种用于在半导体上提供闪存单元的方法和系统。 在一个方面，该方法和系统包括提供多个栅极堆叠并以一定角度提供漏极注入。 多个栅极堆叠限定多个漏极区域和多个源极区域。 该角度是从垂直于半导体表面的方向测量的。 该角度允许多个栅极堆叠阻挡漏极植入物到达多个源极区域。 在另一方面，该方法和系统包括提供多个栅极叠层并以一定角度提供源植入物。 多个栅极堆叠限定多个漏极区域和多个源极区域。 该角度是从垂直于半导体表面的方向测量的。 该角度允许多个栅极堆叠阻挡源植入物到达多个漏极区域。

公开(公告)号：US6127222A

公开(公告)日：2000-10-03

申请号：US991687

申请日：1997-12-16

Applicant: Scott D. Luning ,  Mark Randolph

Inventor： Scott D. Luning ,  Mark Randolph

IPC: H01L21/336

CPC classification number: H01L29/66825

Abstract: A system and method for providing a flash memory cell on a semiconductor substrate are disclosed. The system and method include providing a side implant and providing an implant in at least one of a drain or a source of the flash memory cell.

Abstract translation: 公开了一种用于在半导体衬底上提供闪存单元的系统和方法。 该系统和方法包括提供侧植入物并在闪速存储器单元的漏极或源极中的至少一个中提供植入物。

公开(公告)号：US6015736A

公开(公告)日：2000-01-18

申请号：US993787

申请日：1997-12-19

Applicant: Scott D. Luning ,  Mark Randolph

Inventor： Scott D. Luning ,  Mark Randolph

IPC: H01L21/28 ,  H01L21/26

CPC classification number: H01L21/28273 ,  Y10S438/911 ,  Y10T29/41

Abstract: A system and method for providing at least one memory cell on a semiconductor is disclosed. The method and system include providing a tunneling barrier on the semiconductor, providing at least one floating gate having a corner, and oxidizing the tunneling barrier, a portion of the semiconductor, and the at least one floating gate. A portion of the at least one floating gate including the corner is disposed above the tunneling barrier. The portion of the semiconductor oxidizes at a first rate and at least the corner of the at least one floating gate oxidizes at a second rate. The second rate is sufficiently higher than the first rate to provide a desired thickness of the tunneling barrier a distance from the corner of the at least one floating gate for a particular rounding of the corner of the at least one floating gate.

Abstract translation: 公开了一种在半导体上提供至少一个存储单元的系统和方法。 所述方法和系统包括在半导体上提供隧道势垒，提供至少一个具有拐角的浮动栅极，以及氧化隧道势垒，半导体的一部分和至少一个浮动栅极。 包括拐角的至少一个浮动栅极的一部分设置在隧道势垒上方。 半导体的部分以第一速率氧化，并且至少一个浮栅的至少角部以第二速率氧化。 第二速率足够高于第一速率，以便为至少一个浮动门的拐角的特定四舍五入提供距离至少一个浮动栅极的角的距离的隧道势垒的期望厚度。

公开(公告)号：US07910996B2

公开(公告)日：2011-03-22

申请号：US12496133

申请日：2009-07-01

Applicant: Paul R. Besser ,  Scott D. Luning

Inventor： Paul R. Besser ,  Scott D. Luning

IPC: H01L29/12

CPC classification number: H01L29/66628 ,  H01L29/66772

Abstract: A semiconductor device is disclosed having a conductive gate structure overlying a semiconductor layer having a major surface. An isolation material is recessed within a trench region below the major surface of the semiconductor layer. An epitaxial layer is formed overlying a portion of the major surface and on an active region forming a sidewall of the trench.

Abstract translation: 公开了一种半导体器件，其具有覆盖具有主表面的半导体层的导电栅极结构。 隔离材料凹陷在半导体层的主表面下方的沟槽区域内。 形成外延层，覆盖主表面的一部分和形成沟槽侧壁的有源区。

公开(公告)号：US20090236664A1

公开(公告)日：2009-09-24

申请号：US12471600

申请日：2009-05-26

Applicant: David E. Brown ,  Scott D. Luning

Inventor： David E. Brown ,  Scott D. Luning

IPC: H01L29/786

CPC classification number: H01L29/66545 ,  H01L21/0206 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7833

Abstract: A method for constraining lateral growth of gate caps formed during an epitaxial silicon growth process to achieve raised source/drain regions on poly silicon is presented. The method is appropriate for integration into a manufacturing process for integrated circuit semiconductor devices. The method utilizes selective etch processes, dependant upon the material comprising the protective layer (hard mask) over the gate and the material of the spacers, e.g., oxide mask/nitride spacers, or nitride mask/oxide spacers.

Abstract translation: 提出了一种限制在外延硅生长过程中形成的栅极盖的横向生长以在多晶硅上实现凸起的源极/漏极区域的方法。 该方法适用于集成到集成电路半导体器件的制造工艺中。 该方法利用选择性蚀刻工艺，取决于包含栅极上的保护层（硬掩模）的材料和间隔物的材料，例如氧化物掩模/氮化物间隔物或氮化物掩模/氧化物间隔物。

公开(公告)号：US07553732B1

公开(公告)日：2009-06-30

申请号：US11150923

申请日：2005-06-13

Applicant: David E. Brown ,  Scott D. Luning

Inventor： David E. Brown ,  Scott D. Luning

IPC: H01L21/336

CPC classification number: H01L29/66545 ,  H01L21/0206 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7833

Abstract: A method for constraining lateral growth of gate caps formed during an epitaxial silicon growth process to achieve raised source/drain regions on poly silicon is presented. The method is appropriate for integration into a manufacturing process for integrated circuit semiconductor devices. The method utilizes selective etch processes, dependant upon the material comprising the protective layer (hard mask) over the gate and the material of the spacers, e.g., oxide mask/nitride spacers, or nitride mask/oxide spacers.

Abstract translation: 提出了一种限制在外延硅生长过程中形成的栅极盖的横向生长以在多晶硅上实现凸起的源极/漏极区域的方法。 该方法适用于集成到集成电路半导体器件的制造工艺中。 该方法利用选择性蚀刻工艺，取决于包含栅极上的保护层（硬掩模）的材料和间隔物的材料，例如氧化物掩模/氮化物间隔物或氮化物掩模/氧化物间隔物。

公开(公告)号：US06743685B1

公开(公告)日：2004-06-01

申请号：US09784629

申请日：2001-02-15

Applicant: David D. Wu ,  Michael P. Duane ,  Scott D. Luning

Inventor： David D. Wu ,  Michael P. Duane ,  Scott D. Luning

IPC: H01L21336

CPC classification number: H01L21/28194 ,  H01L21/26586 ,  H01L21/28202 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66492 ,  H01L29/7833

Abstract: A method is provided, the method including forming a gate dielectric above a surface of the substrate and forming a doped-poly gate structure above the gate dielectric, the doped-poly gate structure having an edge region. The method also includes forming a dopant-depleted-poly region in the cage region of the doped-poly gate structure adjacent the gate dielectric.

Abstract translation: 提供了一种方法，所述方法包括在衬底的表面上形成栅极电介质，并在栅极电介质上方形成掺杂多晶硅栅极结构，所述掺杂 - 多晶硅结构具有边缘区域。 该方法还包括在与栅极电介质相邻的掺杂多晶硅栅极结构的笼状区域中形成掺杂剂贫化多晶硅区域。

公开(公告)号：US09048136B2

公开(公告)日：2015-06-02

申请号：US13282261

申请日：2011-10-26

Applicant: Randy W. Mann ,  Scott D. Luning

Inventor： Randy W. Mann ,  Scott D. Luning

IPC: G11C11/00 ,  H01L27/11 ,  H01L27/12 ,  G11C11/412 ,  G11C11/419

CPC classification number: H01L27/1108 ,  G11C11/412 ,  G11C11/419 ,  H01L27/1203

Abstract: A static random access memory cell is provided formed in a silicon layer over a buried oxide layer on a substrate and including first and second inverters each having a pull-up and pull-down transistor configured to form a cell node. Each of the pull-down transistors of the first and second inverters are formed over first regions below the buried oxide layer with the first regions having a first doping level forming first backgates for the pull-down transistors. A pair of passgate transistors respectively couples to the cell nodes of the first and second inverters and each are formed over second regions below the buried oxide layer with the second regions having a second doping level forming second backgates for the passgate transistors. Active bias circuitry applies potentials to the first and second backgates during read, standby and write operations of the static random access memory cell.

Abstract translation: 提供了在衬底上的掩埋氧化物层上的硅层中形成的静态随机存取存储器单元，并且包括第一和第二反相器，每个具有被配置为形成单元节点的上拉和下拉晶体管。 第一和第二反相器的每个下拉晶体管形成在掩埋氧化物层下方的第一区域上，其中第一区域具有形成用于下拉晶体管的第一衬底的第一掺杂级。 一对通道晶体管分别耦合到第一和第二反相器的单元节点，并且每一个均形成在掩埋氧化物层下方的第二区域上，其中第二区域具有形成用于通路晶体管的第二衬底的第二掺杂水平。 主动偏置电路在静态随机存取存储器单元的读取，备用和写入操作期间将电位施加到第一和第二后挡板。