公开(公告)号：US06767770B1

公开(公告)日：2004-07-27

申请号：US10262770

申请日：2002-10-01

Applicant: Andrew Horch ,  Scott Robins ,  Farid Nemati

Inventor： Andrew Horch ,  Scott Robins ,  Farid Nemati

IPC: H01L21332

CPC classification number: H01L29/66242 ,  H01L27/11 ,  H01L29/7436 ,  H01L29/7455

Abstract: A semiconductor memory device having a thyristor is manufactured in a manner that makes possible self-alignment of one or more portions of the thyristor. According to an example embodiment of the present invention, a gate is formed over a first portion of doped substrate. The gate is used to mask a portion of the doped substrate and a second portion of the substrate is doped before or after a spacer is formed. After the second portion of the substrate is doped, the spacer is then formed adjacent to the gate and used to mask the second portion of the substrate while a third portion of the substrate is doped. The gate and spacer are thus used to form self-aligned doped portions of the substrate, wherein the first and second portions form base regions and the third portion form an emitter region of a thyristor. In another implementation, the spacer is also adapted to prevent formation of salicide on the portion of the thyristor beneath the spacer, self-aligning the salicide to the junction between the second and third portions. In addition, dimensions such as width and other characteristics of the doped portions that are used to form a thyristor can be controlled without necessarily using a separate mask.

Abstract translation: 制造具有晶闸管的半导体存储器件以能够使晶闸管的一个或多个部分自对准的方式。 根据本发明的示例性实施例，在掺杂衬底的第一部分上形成栅极。 栅极用于掩模掺杂衬底的一部分，并且衬底的第二部分在形成间隔物之前或之后被掺杂。 在衬底的第二部分被掺杂之后，然后在衬底的第三部分被掺杂的同时，将衬底形成为邻近栅极并用于掩蔽衬底的第二部分。 因此，栅极和间隔物用于形成衬底的自对准掺杂部分，其中第一和第二部分形成基极区，第三部分形成晶闸管的发射极区。 在另一实施方案中，间隔物还适于防止在间隔物下方的可控硅部分上形成自对准硅化物，使自对准硅化物与第二和第三部分之间的连接处。 此外，可以控制用于形成晶闸管的掺杂部分的宽度和其它特性的尺寸，而不必使用单独的掩模。

公开(公告)号：US06756612B1

公开(公告)日：2004-06-29

申请号：US10282331

申请日：2002-10-28

Applicant: Farid Nemati ,  Badredin Fatemizadeh ,  Andrew Horch ,  Scott Robins

Inventor： Farid Nemati ,  Badredin Fatemizadeh ,  Andrew Horch ,  Scott Robins

IPC: H01L2974

CPC classification number: H01L29/41716 ,  H01L27/0817 ,  H01L27/108 ,  H01L27/10844 ,  H01L27/11 ,  H01L29/74

Abstract: Switching times of a thyristor-based semiconductor device are improved by enhancing carrier drainage from a buried thyristor-emitter region. According to an example embodiment of the present invention, a conductive contact extends to a doped well region buried in a substrate and is adapted to drain carriers therefrom. The device includes a thyristor body having at least one doped emitter region buried in the doped well region. A conductive thyristor control port is adapted to capacitively couple to the thyristor body and to control current flow therein. With this approach, the thyristor can be rapidly switched between resistance states, which has been found to be particularly useful in high-speed data latching implementations including but not limited to memory cell applications.

Abstract translation: 通过增强从掩埋晶闸管 - 发射极区域的载流子排放，可以改善晶闸管基半导体器件的开关时间。 根据本发明的示例性实施例，导电接触延伸到掩埋在衬底中的掺杂阱区，并且适于从其引出载流子。 该器件包括晶体管本体，其具有埋在掺杂阱区中的至少一个掺杂射极区。 导电晶闸管控制端口适于电容耦合到晶闸管主体并控制其中的电流。 通过这种方法，晶闸管可以在电阻状态之间快速切换，这已经被发现在包括但不限于存储器单元应用的高速数据锁存实现中特别有用。

公开(公告)号：US06666481B1

公开(公告)日：2003-12-23

申请号：US10262728

申请日：2002-10-01

Applicant: Andrew Horch ,  Scott Robins

Inventor： Andrew Horch ,  Scott Robins

IPC: H01L29423

CPC classification number: H01L29/41716 ,  Y10S977/70

Abstract: A semiconductor device is formed having a thyristor, a pass device and a conductive shunt that electrically connects an emitter region of the thyristor with a node near an upper surface of the substrate. In one example embodiment of the present invention, the conductive shunt is formed in a trench in a substrate and extending from an upper surface of the substrate to an emitter region of a vertical thyristor, with the emitter region being in the substrate and below the upper surface. In one implementation, the thyristor includes a thyristor body and a control port, with an N+ emitter region of the thyristor body being in the substrate and below and upper surface thereof. A pass device is formed adjacent to the thyristor, and the conductive shunt is formed in a trench extending from the N+ emitter region to a source/drain region of the pass device. With this approach, thyristor applications can be implemented having an emitter region in a substrate and not necessarily directly accessible, for example, via an upper surface of the substrate. This approach is also useful, for example, in applications where a cathode-down thyristor is used, such as when it is desirable to form the thyristor control port near a bottom portion of the thyristor, and in high-density circuit applications, such as memory arrays.

Abstract translation: 形成半导体器件，其具有将晶闸管的发射极区域与衬底的上表面附近的节点电连接的晶闸管，通过器件和导电分流器。 在本发明的一个示例实施例中，导电分流器形成在衬底中的沟槽中并且从衬底的上表面延伸到垂直晶闸管的发射极区域，其中发射极区域在衬底中并且在上部 表面。 在一个实施方案中，晶闸管包括晶闸管主体和控制端口，晶闸管主体的N +发射极区域位于衬底中并且其下表面和上表面。 形成与晶闸管相邻的通过器件，并且导电分流器形成在从N +发射极区域延伸到通过器件的源极/漏极区域的沟槽中。 利用这种方法，可以实现晶闸管应用，其在衬底中具有发射极区域，并且不一定直接可访问，例如经由衬底的上表面。 这种方法在例如使用阴极 - 下降晶闸管的应用中也是有用的，例如当期望在晶闸管的底部附近形成晶闸管控制端口时，以及在高密度电路应用中，例如 存储器阵列。

公开(公告)号：US06653175B1

公开(公告)日：2003-11-25

申请号：US10231805

申请日：2002-08-28

Applicant: Farid Nemati ,  Hyun-Jin Cho ,  Scott Robins

Inventor： Farid Nemati ,  Hyun-Jin Cho ,  Scott Robins

IPC: H01L21332

CPC classification number: G11C11/39 ,  H01L29/7436 ,  H01L29/749

Abstract: A semiconductor device having a thyristor-based memory device exhibits improved stability under adverse operating conditions related to temperature, noise, electrical disturbances and light. In one particular example embodiment of the present invention, a semiconductor device includes a thyristor-based memory device that uses a shunt that effects a leakage current in the thyristor. The thyristor includes a capacitively-coupled control port and anode and cathode end portions. Each of the end portions has an emitter region and an adjacent base region. In one implementation, the current shunt is located between the emitter and base region of one of the end portions of the thyristor and is configured and arranged to shunt low-level current therebetween. In connection with an example embodiment, it has been discovered that shunting current in this manner improves the ability of the device to operate under adverse conditions that would, absent the shunt, result in inadvertent turn on, while keeping the standby current of the memory device to an acceptably low level.

Abstract translation: 具有基于晶闸管的存储器件的半导体器件在与温度，噪声，电扰动和光线相关的不利操作条件下表现出改进的稳定性。 在本发明的一个具体示例实施例中，半导体器件包括基于晶闸管的存储器件，其使用在晶闸管中产生漏电流的分流器。 晶闸管包括电容耦合控制端口和阳极和阴极端部分。 每个端部具有发射极区域和相邻的基极区域。 在一个实施方案中，电流分流器位于晶闸管的一个端部的发射极和基极区域之间，并且被配置和布置成在它们之间分流低电平电流。 结合示例性实施例，已经发现，以这种方式分流电流提高了器件在不利条件下操作的能力，这种不利条件将在不存在分流的情况下导致无意中导通，同时保持存储器件的待机电流 达到可接受的低水平。

公开(公告)号：US06653174B1

公开(公告)日：2003-11-25

申请号：US10023052

申请日：2001-12-17

Applicant: Hyun-Jin Cho ,  Andrew Horch ,  Scott Robins ,  Farid Nemati

Inventor： Hyun-Jin Cho ,  Andrew Horch ,  Scott Robins ,  Farid Nemati

IPC: H01L21332

CPC classification number: H01L29/74 ,  G11C11/39 ,  H01L27/0617 ,  H01L27/0688 ,  H01L27/1023 ,  H01L27/1027 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/41716 ,  H01L29/42308 ,  H01L29/749 ,  H01L29/87

Abstract: A semiconductor device having a thyristor is manufactured in a manner that reduces or eliminates manufacturing difficulties commonly experienced in the formation of such devices. According to an example embodiment of the present invention, a thyristor is formed having some or all of the body of the thyristor extending above a substrate surface of a semiconductor device. The semiconductor device includes at least one transistor having source/drain regions formed in the substrate prior to the formation of the thyristor. One or more layers of material are deposited on the substrate surface and used to form a portion of a body of the thyristor that includes anode and cathode end portions. Each end portion is formed having a base region and an emitter region, and at least one of the end portions includes a portion that is in the substrate and electrically coupled to the transistor. A control port is formed capacitively coupled to at least one of the base regions.

Abstract translation: 制造具有晶闸管的半导体器件以减少或消除在形成这些器件时通常经历的制造困难的方式。 根据本发明的示例性实施例，形成了晶闸管，其中半导体器件的衬底表面上方延伸有晶闸管的一部分或全部。 半导体器件包括至少一个晶体管，其在形成晶闸管之前在衬底中形成有源/漏区。 一层或多层材料沉积在衬底表面上，并用于形成包括阳极和阴极端部的晶闸管体的一部分。 每个端部形成为具有基极区域和发射极区域，并且至少一个端部部分包括位于衬底中并电耦合到晶体管的部分。 形成电容耦合到至少一个基极区域的控制端口。

公开(公告)号：US07859011B2

公开(公告)日：2010-12-28

申请号：US12368171

申请日：2009-02-09

Applicant: Zachary K. Lee ,  Farid Nemati ,  Scott Robins

Inventor： Zachary K. Lee ,  Farid Nemati ,  Scott Robins

IPC: H01L29/74

CPC classification number: H01L27/1203 ,  H01L29/7841

Abstract: A semiconductor device may comprise a partially-depleted SOI MOSFET having a floating body region disposed between a source and drain. The floating body region may be driven to receive injected carriers for adjusting its potential during operation of the MOSFET. In a particular case, the MOSFET may comprise another region of semiconductor material in contiguous relationship with a drain/source region of the MOSFET and on a side thereof opposite to the body region. This additional region may be formed with a conductivity of type opposite the drain/source, and may establish an effective bipolar device per the body, the drain/source and the additional region. The geometries and doping thereof may be designed to establish a transport gain of magnitude sufficient to assist the injection of carriers into the floating body region, yet small enough to guard against inter-latching with the MOSFET.

Abstract translation: 半导体器件可以包括部分耗尽的SOI MOSFET，其具有设置在源极和漏极之间的浮体区域。 可以驱动浮体区域以接收注入的载流子，以在MOSFET的操作期间调整其电位。 在特定的情况下，MOSFET可以包括与MOSFET的漏极/源极区域和与体区域相对的一侧连续关系的半导体材料的另一区域。 该附加区域可以形成为具有与漏极/源极相反的类型的导电性，并且可以建立每个主体，漏极/源极和附加区域的有效双极器件。 其几何形状和掺杂可被设计成建立足以帮助载流子注入浮体区域的传输增益，但足够小以防止与MOSFET的互锁。

公开(公告)号：US07554130B1

公开(公告)日：2009-06-30

申请号：US11361869

申请日：2006-02-23

Applicant: Scott Robins ,  Kevin J. Yang ,  Rajesh N. Gupta

Inventor： Scott Robins ,  Kevin J. Yang ,  Rajesh N. Gupta

IPC: H01L29/74

CPC classification number: H01L27/1027 ,  H01L29/7436

Abstract: An integrated circuit having memory, including thyristor-based memory cells, is described, where each of the thyristor-based memory cells includes a thyristor-based storage element and an access transistor. Where the thyristor-based storage element includes an anode region and a cathode region, a pair of the thyristor-based memory cells are commonly coupled via a bitline associated with the access transistor or via a reference voltage line coupled to the anode region. Bitline or anode regions are separated from one another by an isolation region. In another configuration, a bitline region has a locally implant-damaged region to inhibit charge transfer between the pair. In yet another configuration, a storage node contact or contacts respectively can extend over or are coupled to a storage node line extending over an isolation region. In this latter configuration, a source/drain region and the cathode region are separated from one another by an isolation region.

Abstract translation: 描述了一种具有存储器的集成电路，包括基于晶闸管的存储单元，其中每个基于晶闸管的存储单元包括基于晶闸管的存储元件和存取晶体管。 在基于晶闸管的存储元件包括阳极区域和阴极区域的情况下，一对基于晶闸管的存储单元通常经由与存取晶体管相关联的位线或经由耦合到阳极区域的参考电压线耦合。 位线或阳极区域通过隔离区域彼此分离。 在另一种配置中，位线区域具有局部注入损坏区域，以阻止该对之间的电荷转移。 在另一种配置中，存储节点接触点或触头分别可以延伸超过或耦合到在隔离区域上延伸的存储节点线。 在后一种配置中，源极/漏极区域和阴极区域通过隔离区域彼此分离。

公开(公告)号：US07374974B1

公开(公告)日：2008-05-20

申请号：US10794843

申请日：2004-03-05

Applicant: Andrew Horch ,  Scott Robins

Inventor： Andrew Horch ,  Scott Robins

IPC: H01L21/332

CPC classification number: H01L29/749 ,  H01L29/66378 ,  H01L29/742

Abstract: A thyristor-based semiconductor device includes a thyristor body that has at least one region in the substrate and a thyristor control port in a trenched region of the device substrate. According to an example embodiment of the present invention, the trench is at least partially filled with a dielectric material and a control port adapted to capacitively couple to the at least one thyristor body region in the substrate. In a more specific implementation, the dielectric material includes deposited dielectric material that is adapted to exhibit resistance to voltage-induced stress that thermally-grown dielectric materials generally exhibit. In another implementation, the dielectric material includes thermally-grown dielectric material, and when used in connection with highly-doped material in the trench, grows faster on the highly-doped material than on a sidewall of the trench that faces the at least on thyristor body region in the substrate. In still another implementation, the dielectric material includes both a thermally-grown dielectric material and a deposited dielectric material. These approaches are particularly useful, for example, in high-density and other applications where thermally-stable dielectric materials are desirable and/or where dielectric material growth at different rates is desirable.

Abstract translation: 基于晶闸管的半导体器件包括晶体管本体，其在衬底中具有至少一个区域，并且在器件衬底的沟槽区域中具有晶闸管控制端口。 根据本发明的示例实施例，沟槽至少部分地填充有电介质材料和适于电容耦合到衬底中的至少一个可控硅体区域的控制端口。 在更具体的实施方案中，电介质材料包括沉积的电介质材料，其适于显示耐热生长的电介质材料通常表现出的电压诱发应力。 在另一个实施方案中，电介质材料包括热生长的介电材料，并且当与沟槽中的高度掺杂材料结合使用时，在高掺杂材料上比在面向至少可控硅的沟槽的侧壁上生长得更快 基体中的体区。 在另一个实施方式中，电介质材料包括热生长介电材料和沉积的电介质材料。 这些方法特别有用，例如在高密度和其他需要热稳定介电材料的应用中，和/或其中需要不同速率的介电材料生长。

公开(公告)号：US07183591B1

公开(公告)日：2007-02-27

申请号：US11238773

申请日：2005-09-29

Applicant: Andrew Horch ,  Scott Robins

Inventor： Andrew Horch ,  Scott Robins

IPC: H01L29/74 ,  H01L27/102

CPC classification number: H01L27/0629 ,  H01L27/0817 ,  H01L29/74

Abstract: A semiconductor device includes a thyristor body having at least one region in a substrate. According to an example embodiment of the present invention, a trench is in a substrate and adjacent to a thyristor body region in the substrate. The trench is lined with an insulative material and further includes conductive material that is insulated from the thyristor body region in the substrate by the liner material. A conductive thyristor control port is located in the trench and adapted for capacitively coupling to the thyristor body region in the substrate and to control current in the thyristor body by causing an outflow of minority carriers in the thyristor. With this approach, conductive material can be used to fill a portion of the trench while using the trench portion including the conductive material to electrically isolate a portion of the thyristor body in the substrate. This approach is particularly useful, for example, in high-density applications where insulative trenches having high aspect ratios are desired.

Abstract translation: 半导体器件包括在衬底中具有至少一个区域的晶闸管本体。 根据本发明的示例性实施例，沟槽在衬底中并且与衬底中的可控硅体区相邻。 沟槽衬有绝缘材料，并且还包括通过衬垫材料与衬底中的可控硅体区域绝缘​​的导电材料。 导电晶闸管控制端口位于沟槽中，适于电容耦合到衬底中的晶闸管本体区域，并通过引起晶闸管中少数载流子的流出来控制晶闸管主体中的电流。 利用这种方法，可以使用导电材料来填充沟槽的一部分，同时使用包括导电材料的沟槽部分来电隔离衬底中的可控硅体的一部分。 这种方法特别有用，例如在需要具有高纵横比的绝缘沟槽的高密度应用中。

公开(公告)号：US07109532B1

公开(公告)日：2006-09-19

申请号：US10746758

申请日：2003-12-23

Applicant: Zachary K. Lee ,  Farid Nemati ,  Scott Robins

Inventor： Zachary K. Lee ,  Farid Nemati ,  Scott Robins

IPC: H01L29/74 ,  H01L27/12

CPC classification number: H01L27/1203 ,  H01L29/7841

Abstract: A semiconductor device may comprise a partially-depleted SOI MOSFET having a floating body region disposed between a source and drain. The floating body region may be driven to receive injected carriers for adjusting its potential during operation of the MOSFET. In a particular case, the MOSFET may comprise another region of semiconductor material in contiguous relationship with a drain/source region of the MOSFET and on a side thereof opposite to the body region. This additional region may be formed with a conductivity of type opposite the drain/source, and may establish an effective bipolar device per the body, the drain/source and the additional region. The geometries and doping thereof may be designed to establish a transport gain of magnitude sufficient to assist the injection of carriers into the floating body region, yet small enough to guard against inter-latching with the MOSFET.