公开(公告)号：US06756612B1

公开(公告)日：2004-06-29

申请号：US10282331

申请日：2002-10-28

申请人： Farid Nemati ,  Badredin Fatemizadeh ,  Andrew Horch ,  Scott Robins

发明人： Farid Nemati ,  Badredin Fatemizadeh ,  Andrew Horch ,  Scott Robins

IPC分类号： H01L2974

CPC分类号： H01L29/41716 ,  H01L27/0817 ,  H01L27/108 ,  H01L27/10844 ,  H01L27/11 ,  H01L29/74

摘要： Switching times of a thyristor-based semiconductor device are improved by enhancing carrier drainage from a buried thyristor-emitter region. According to an example embodiment of the present invention, a conductive contact extends to a doped well region buried in a substrate and is adapted to drain carriers therefrom. The device includes a thyristor body having at least one doped emitter region buried in the doped well region. A conductive thyristor control port is adapted to capacitively couple to the thyristor body and to control current flow therein. With this approach, the thyristor can be rapidly switched between resistance states, which has been found to be particularly useful in high-speed data latching implementations including but not limited to memory cell applications.

摘要翻译： 通过增强从掩埋晶闸管 - 发射极区域的载流子排放，可以改善晶闸管基半导体器件的开关时间。 根据本发明的示例性实施例，导电接触延伸到掩埋在衬底中的掺杂阱区，并且适于从其引出载流子。 该器件包括晶体管本体，其具有埋在掺杂阱区中的至少一个掺杂射极区。 导电晶闸管控制端口适于电容耦合到晶闸管主体并控制其中的电流。 通过这种方法，晶闸管可以在电阻状态之间快速切换，这已经被发现在包括但不限于存储器单元应用的高速数据锁存实现中特别有用。

公开(公告)号：US06872602B1

公开(公告)日：2005-03-29

申请号：US10785166

申请日：2004-02-23

申请人： Farid Nemati ,  Badredin Fatemizadeh ,  Andrew Horch ,  Scott Robins

发明人： Farid Nemati ,  Badredin Fatemizadeh ,  Andrew Horch ,  Scott Robins

IPC分类号： H01L21/8242 ,  H01L21/8244 ,  H01L27/08 ,  H01L27/108 ,  H01L27/11 ,  H01L29/417 ,  H01L29/74 ,  H01L21/332

CPC分类号： H01L29/41716 ,  H01L27/0817 ,  H01L27/108 ,  H01L27/10844 ,  H01L27/11 ,  H01L29/74

摘要： Switching times of a thyristor-based semiconductor device are improved by enhancing carrier drainage from a buried thyristor-emitter region. According to an example embodiment of the present invention, a conductive contact extends to a doped well region buried in a substrate and is adapted to drain carriers therefrom. The device includes a thyristor body having at least one doped emitter region buried in the doped well region. A conductive thyristor control port is adapted to capacitively couple to the thyristor body and to control current flow therein. With this approach, the thyristor can be rapidly switched between resistance states, which has been found to be particularly useful in high-speed data latching implementations including but not limited to memory cell applications.

摘要翻译： 通过增强从掩埋晶闸管 - 发射极区域的载流子排放，可以改善晶闸管基半导体器件的开关时间。 根据本发明的示例性实施例，导电接触延伸到掩埋在衬底中的掺杂阱区，并且适于从其引出载流子。 该器件包括晶体管本体，其具有埋在掺杂阱区中的至少一个掺杂射极区。 导电晶闸管控制端口适于电容耦合到晶闸管主体并控制其中的电流。 通过这种方法，晶闸管可以在电阻状态之间快速切换，这已经被发现在包括但不限于存储器单元应用的高速数据锁存实现中特别有用。

公开(公告)号：US20130109143A1

公开(公告)日：2013-05-02

申请号：US13572281

申请日：2012-08-10

申请人： Marco A. Zuniga ,  Yang Lu ,  Badredin Fatemizadeh ,  Jayasimha Prasad ,  Amit Paul ,  Jun Ruan ,  John Xia

发明人： Marco A. Zuniga ,  Yang Lu ,  Badredin Fatemizadeh ,  Jayasimha Prasad ,  Amit Paul ,  Jun Ruan ,  John Xia

IPC分类号： H01L29/78

CPC分类号： H01L29/66704 ,  H01L21/265 ,  H01L21/28105 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/0626 ,  H01L29/063 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66696 ,  H01L29/78 ,  H01L29/7802 ,  H01L29/7825 ,  H01L29/7827 ,  H01L29/7835

摘要： The present application features methods of fabricating a gate region in a vertical laterally diffused metal oxide semiconductor (LDMOS) transistor. In one aspect, a method includes depositing a masking layer on an n-well region implanted on a substrate, patterning the masking layer to define an area, and forming a first trench in the area such that a length of the first trench extends from a surface of the n-well region to a first depth in the n-well region. The method also includes filling the first trench by a conductive material and depositing a layer of oxide over the area. The method further includes etching out at least a portion of the oxide layer to expose a portion of the conductive material, removing the conductive material from the exposed portion to form a second trench, and filling the second trench with an oxide to form an asymmetric gate of the transistor.

摘要翻译： 本申请的特征在于在垂直横向扩散的金属氧化物半导体（LDMOS）晶体管中制造栅极区域的方法。 在一个方面，一种方法包括在植入在衬底上的n阱区域上沉积掩模层，图案化掩模层以限定区域，以及在该区域中形成第一沟槽，使得第一沟槽的长度从 n阱区域的表面到n阱区域中的第一深度。 该方法还包括通过导电材料填充第一沟槽并在该区域上沉积一层氧化物。 该方法还包括蚀刻掉氧化物层的至少一部分以暴露导电材料的一部分，从暴露部分去除导电材料以形成第二沟槽，并用氧化物填充第二沟槽以形成非对称栅极 的晶体管。

公开(公告)号：US10147801B2

公开(公告)日：2018-12-04

申请号：US13572110

申请日：2012-08-10

申请人： Marco A. Zuniga ,  Yang Lu ,  Badredin Fatemizadeh ,  Jayasimha Prasad ,  Amit Paul ,  Jun Ruan

发明人： Marco A. Zuniga ,  Yang Lu ,  Badredin Fatemizadeh ,  Jayasimha Prasad ,  Amit Paul ,  Jun Ruan

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/265 ,  H01L21/28 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/08 ,  H01L29/10

摘要： The present application features a transistor that includes an n-well region implanted into a surface of a substrate, a gate region, and a source region, and a drain region. The source region is on a first side of the gate region and includes a p-body region in the n-well region. An n+ region and a p+ region are implanted in the p-body region such that the p+ region is below the n+ region. The drain region is on a second side of the gate region and includes an n+ region.

公开(公告)号：US20130105887A1

公开(公告)日：2013-05-02

申请号：US13572015

申请日：2012-08-10

申请人： Marco A. Zuniga ,  Yang Lu ,  Badredin Fatemizadeh ,  Jayasimha Prasad ,  Amit Paul ,  Jun Ruan

发明人： Marco A. Zuniga ,  Yang Lu ,  Badredin Fatemizadeh ,  Jayasimha Prasad ,  Amit Paul ,  Jun Ruan

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/66704 ,  H01L21/265 ,  H01L21/28105 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/0626 ,  H01L29/063 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66696 ,  H01L29/78 ,  H01L29/7802 ,  H01L29/7825 ,  H01L29/7827 ,  H01L29/7835

摘要： Described here are transistors and fabrication methods thereof. In one implementation, a transistor includes an n-well region implanted into a surface of a substrate, and a trench in the n-well region. The trench extends from the surface to a first depth. The trench includes a gate of conductive material in the trench, and dielectric material filling a volume of the trench not filled by the conductive material. The transistor also includes a p-type material in a first region extending from a second depth to a third depth, the second depth and the third depth being greater than the first depth. The transistor further includes a source region and a drain region.

摘要翻译： 这里描述的是晶体管及其制造方法。 在一个实施方式中，晶体管包括注入到衬底的表面中的n阱区域和n阱区域中的沟槽。 沟槽从表面延伸到第一深度。 沟槽包括在沟槽中的导电材料的栅极，以及填充未被导电材料填充的一定体积的电介质材料。 晶体管还包括在从第二深度延伸到第三深度的第一区域中的p型材料，第二深度和第三深度大于第一深度。 晶体管还包括源极区和漏极区。

公开(公告)号：US20130105888A1

公开(公告)日：2013-05-02

申请号：US13572110

申请日：2012-08-10

申请人： Marco A. Zuniga ,  Yang Lu ,  Badredin Fatemizadeh ,  Jayasimha Prasad ,  Amit Paul ,  Jun Ruan

发明人： Marco A. Zuniga ,  Yang Lu ,  Badredin Fatemizadeh ,  Jayasimha Prasad ,  Amit Paul ,  Jun Ruan

IPC分类号： H01L29/78

CPC分类号： H01L29/66704 ,  H01L21/265 ,  H01L21/28105 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/0626 ,  H01L29/063 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66696 ,  H01L29/78 ,  H01L29/7802 ,  H01L29/7825 ,  H01L29/7827 ,  H01L29/7835

摘要： The present application features a transistor that includes an n-well region implanted into a surface of a substrate, a gate region, and a source region, and a drain region. The source region is on a first side of the gate region and includes a p-body region in the n-well region. An n+ region and a p+ region are implanted in the p-body region such that the p+ region is below the n+ region. The drain region is on a second side of the gate region and includes an n+ region.

摘要翻译： 本申请的特征在于一种晶体管，其包括注入到衬底，栅极区域和源极区域以及漏极区域的表面中的n阱区域。 源极区域在栅极区域的第一侧上，并且在n阱区域中包括p体区域。 在p体区域注入n +区域和p +区域，使得p +区域低于n +区域。 漏极区域在栅极区域的第二侧上并且包括n +区域。

公开(公告)号：US07049677B2

公开(公告)日：2006-05-23

申请号：US10767384

申请日：2004-01-28

申请人： Badredin Fatemizadeh ,  Ali Salih

发明人： Badredin Fatemizadeh ,  Ali Salih

IPC分类号： H01L29/00

CPC分类号： H01L29/7813 ,  H01L21/76283 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/1203

摘要： A semiconductor device has a driver device (10) in proximity to a power device (12). In making the semiconductor device, an N+ layer (24) is formed on a substrate (22). A portion of the N+ layer is removed, substantially down to the substrate, to provide a layer offset (28) between the driver device area and power device area. An epi region of uniform thickness is formed over the driver device and power device areas. A portion of the epi layer is removed to provide another layer offset (70). An oxide layer (68) of uniform thickness is formed over the epi region. The oxide layer is planarized to remove oxide layer over the N+ layer. An oxide-filled trench (80) is formed between the driver device and the power device. The oxide-filled trench extends down to the oxide layer to isolate the driver device from the power device.

摘要翻译： 半导体器件具有靠近功率器件（12）的驱动器器件（10）。 在制造半导体器件时，在衬底（22）上形成N +层（24）。 N +层的一部分基本上被去除到衬底，以在驱动器器件区域和功率器件区域之间提供层偏移（28）。 在驱动器设备和功率器件区域上形成均匀厚度的外延区域。 去除外延层的一部分以提供另一层偏移（70）。 在epi区域上形成均匀厚度的氧化物层（68）。 将氧化物层平坦化以除去N +层上的氧化物层。 在驱动器装置和功率装置之间形成氧化物填充的沟槽（80）。 氧化物填充的沟槽向下延伸到氧化物层以将驱动器器件与功率器件隔离。

公开(公告)号：US20050040459A1

公开(公告)日：2005-02-24

申请号：US10647029

申请日：2003-08-22

申请人： John Amato ,  Badredin Fatemizadeh ,  Ali Salih ,  Shamsul Khan

发明人： John Amato ,  Badredin Fatemizadeh ,  Ali Salih ,  Shamsul Khan

IPC分类号： H01L20060101 ,  H01L21/336 ,  H01L29/423 ,  H01L29/76 ,  H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/4236 ,  H01L29/4238

摘要： A closed cell trench power MOSFET has a trench (54) running in first and second perpendicular directions through a body region (48) and extending into an epitaxial region (46). The trenches meet to form intersections (16). A polysilicon layer (58) is deposited in the trench. A photoresist pattern (60) is formed over the intersections to inhibit removal of the conductive material from the trench in and around the intersection areas. The process of inhibiting removal of the conductive material over the intersection areas of the trench prevents formation of a depression in the polysilicon in and around the intersection which would increase resistivity in the gate region. The goal of preventing formation of depressions in the polysilicon can also be achieved by making the polysilicon thicker on the intersections prior to the etching process and by making the trenches narrower in and around the intersections.

摘要翻译： 闭孔沟槽功率MOSFET具有穿过体区（48）的第一和第二垂直方向上延伸并延伸到外延区域（46）中的沟槽（54）。 壕沟相交，形成十字路口（16）。 多晶硅层（58）沉积在沟槽中。 在交叉点之上形成光致抗蚀剂图案（60），以阻止导电材料从交叉区域内和周围的沟槽移除。 阻止在沟槽的交叉区域上去除导电材料的过程防止在交叉点中和周围的多晶硅中形成凹陷，这将增加栅极区域中的电阻率。 防止在多晶硅中形成凹陷的目的还可以通过在蚀刻工艺之前使交叉点上的多晶硅变厚，并且通过在交叉点内和周围使沟槽变窄来实现。

公开(公告)号：US08866217B2

公开(公告)日：2014-10-21

申请号：US13572015

申请日：2012-08-10

申请人： Marco A. Zuniga ,  Yang Lu ,  Badredin Fatemizadeh ,  Jayasimha Prasad ,  Amit Paul ,  Jun Ruan

发明人： Marco A. Zuniga ,  Yang Lu ,  Badredin Fatemizadeh ,  Jayasimha Prasad ,  Amit Paul ,  Jun Ruan

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/66704 ,  H01L21/265 ,  H01L21/28105 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/0626 ,  H01L29/063 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66696 ,  H01L29/78 ,  H01L29/7802 ,  H01L29/7825 ,  H01L29/7827 ,  H01L29/7835

摘要： Described here are transistors and fabrication methods thereof. In one implementation, a transistor includes an n-well region implanted into a surface of a substrate, and a trench in the n-well region. The trench extends from the surface to a first depth. The trench includes a gate of conductive material in the trench, and dielectric material filling a volume of the trench not filled by the conductive material. The transistor also includes a p-type material in a first region extending from a second depth to a third depth, the second depth and the third depth being greater than the first depth. The transistor further includes a source region and a drain region.

摘要翻译： 这里描述的是晶体管及其制造方法。 在一个实施方式中，晶体管包括注入到衬底的表面中的n阱区域和n阱区域中的沟槽。 沟槽从表面延伸到第一深度。 沟槽包括在沟槽中的导电材料的栅极，以及填充未被导电材料填充的一定体积的电介质材料。 晶体管还包括在从第二深度延伸到第三深度的第一区域中的p型材料，第二深度和第三深度大于第一深度。 晶体管还包括源极区和漏极区。

公开(公告)号：US08647950B2

公开(公告)日：2014-02-11

申请号：US13572428

申请日：2012-08-10

申请人： Marco A. Zuniga ,  Yang Lu ,  Badredin Fatemizadeh ,  Jayasimha Prasad ,  Amit Paul ,  Jun Ruan

发明人： Marco A. Zuniga ,  Yang Lu ,  Badredin Fatemizadeh ,  Jayasimha Prasad ,  Amit Paul ,  Jun Ruan

IPC分类号： H01L21/336

CPC分类号： H01L29/66704 ,  H01L21/265 ,  H01L21/28105 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/0626 ,  H01L29/063 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66696 ,  H01L29/78 ,  H01L29/7802 ,  H01L29/7825 ,  H01L29/7827 ,  H01L29/7835

摘要： A method of fabricating a vertical gate region in LDMOS transistor includes depositing a first masking layer on an n-well region implanted on a substrate, patterning the first masking layer to define an area, depositing a second masking layer over the area, etching through the second masking layer in a first portion of the area to expose the n-well region, and etching the exposed n-well region to form a first trench. The first trench, extending from a surface of the n-well region to a first depth, is filled with an oxide. The second masking layer is etched through in a second portion of the area to expose the n-well region. A second trench is formed in the n-well, the second trench extending from the surface to a second depth, less than the first depth. An asymmetric vertical gate is formed by filling the second trench with a conductive material.

摘要翻译： 一种在LDMOS晶体管中制造垂直栅极区域的方法，包括在植入在衬底上的n阱区域上沉积第一掩模层，图案化第一掩模层以限定区域，在该区域上沉积第二掩模层， 在所述区域的第一部分中的第二掩模层以暴露所述n阱区域，以及蚀刻所暴露的n阱区域以形成第一沟槽。 从n阱区域的表面延伸到第一深度的第一沟槽被填充有氧化物。 在该区域的第二部分中蚀刻第二掩模层以暴露n阱区域。 在n阱中形成第二沟槽，第二沟槽从表面延伸到第二深度，小于第一深度。 通过用导电材料填充第二沟槽来形成非对称垂直栅极。