公开(公告)号：US20140003140A1

公开(公告)日：2014-01-02

申请号：US13535048

申请日：2012-06-27

Applicant: Rajesh N. Gupta

Inventor： Rajesh N. Gupta

IPC: G11C11/39

CPC classification number: G11C11/39 ,  B82Y10/00 ,  G11C7/00

Abstract: Apparatuses and methods can include write schemes for a thyristor memory cell in which an access pulse applied to the gate of the thyristor memory cell is adjusted relative to the data pulse to write data into the thyristor memory cell. Some of the write schemes may substantially reduce or eliminate an unselected data line disturb. In various embodiments, the thyristor memory cell can be structured with two control nodes and its cathode or anode coupled to a reference voltage node common to all thyristor memory cells in a memory array. Additional apparatuses and methods are disclosed.

Abstract translation: 装置和方法可以包括用于晶闸管存储单元的写入方案，其中施加到晶闸管存储单元的栅极的访问脉冲相对于数据脉冲被调整以将数据写入晶闸管存储单元。 一些写入方案可以显着地减少或消除未选择的数据线干扰。 在各种实施例中，晶闸管存储单元可以由两个控制节点构成，其阴极或阳极耦合到存储器阵列中所有可控硅存储器单元公共的参考电压节点。 公开了附加的装置和方法。

公开(公告)号：US20130182486A1

公开(公告)日：2013-07-18

申请号：US13350061

申请日：2012-01-13

Applicant: Rajesh N. Gupta ,  Farid Nemati

Inventor： Rajesh N. Gupta ,  Farid Nemati

IPC: G11C11/21 ,  H01L21/8239

CPC classification number: H01L27/2454 ,  G11C11/161 ,  G11C11/1659 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1608

Abstract: Arrays of memory cells having a common gate terminal and methods of operating and forming the same are described herein. As an example, an array of memory cells may include a group of memory cells each having a resistive storage element coupled to a select device. Each select device includes a first terminal, a second terminal, and a gate terminal, where the gate terminal is common to each memory cell of the group.

公开(公告)号：US07491586B2

公开(公告)日：2009-02-17

申请号：US11159514

申请日：2005-06-22

Applicant: Andrew E Horch ,  Hyun-Jin Cho ,  Farid Nemati ,  Scott Robins ,  Rajesh N. Gupta ,  Kevin J. Yang

Inventor： Andrew E Horch ,  Hyun-Jin Cho ,  Farid Nemati ,  Scott Robins ,  Rajesh N. Gupta ,  Kevin J. Yang

IPC: H01L21/332 ,  H01L21/04 ,  H01L21/425

CPC classification number: G11C11/39 ,  H01L27/0817 ,  H01L29/7436 ,  H01L29/7455 ,  H01L29/749

Abstract: A method of fabricating a thyristor-based memory may include forming different opposite conductivity-type regions in silicon for defining a thyristor and an access device in series relationship. An activation anneal may activate dopants previously implanted for the different regions. A damaging implant of germanium or xenon or argon may be directed into select regions of the silicon including at least one p-n junction region for the access device and the thyristor. A re-crystallization anneal may then be performed to re-crystallize at least some of the damaged lattice structure resulting from the damaging implant. The re-crystallization anneal may use a temperature less than that of the previous activation anneal.

Abstract translation: 制造基于晶闸管的存储器的方法可以包括在硅中形成用于限定可控硅和串联连接的存取装置的不同的相反导电型区域。 激活退火可以激活先前为不同区域植入的掺杂剂。 可以将锗或氙或氩的有害植入物引导到硅的选择区域中，包括用于进入装置和晶闸管的至少一个p-n结区域。 然后可以进行重结晶退火，以重新结晶由损伤性植入物引起的至少一些损伤的晶格结构。 再结晶退火可以使用比先前激活退火的温度低的温度。

公开(公告)号：US09082494B2

公开(公告)日：2015-07-14

申请号：US13350061

申请日：2012-01-13

Applicant: Rajesh N. Gupta ,  Farid Nemati

Inventor： Rajesh N. Gupta ,  Farid Nemati

IPC: G11C11/00 ,  G11C11/16 ,  H01L45/00 ,  H01L27/22 ,  H01L27/24

CPC classification number: H01L27/2454 ,  G11C11/161 ,  G11C11/1659 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1608

Abstract: Arrays of memory cells having a common gate terminal and methods of operating and forming the same are described herein. As an example, an array of memory cells may include a group of memory cells each having a resistive storage element coupled to a select device. Each select device includes a first terminal, a second terminal, and a gate terminal, where the gate terminal is common to each memory cell of the group.

Abstract translation: 这里描述了具有公共栅极端子的存储单元阵列及其操作和形成方法。 作为示例，存储器单元阵列可以包括一组存储器单元，每个存储单元具有耦合到选择器件的电阻存储元件。 每个选择装置包括第一端子，第二端子和栅极端子，其中栅极端子对于该组的每个存储器单元是公用的。

公开(公告)号：US08797794B2

公开(公告)日：2014-08-05

申请号：US13535048

申请日：2012-06-27

Applicant: Rajesh N. Gupta

Inventor： Rajesh N. Gupta

IPC: G11C11/34 ,  G11C11/39 ,  B82Y10/00

CPC classification number: G11C11/39 ,  B82Y10/00 ,  G11C7/00

Abstract: Apparatuses and methods can include write schemes for a thyristor memory cell in which an access pulse applied to the gate of the thyristor memory cell is adjusted relative to the data pulse to write data into the thyristor memory cell. Some of the write schemes may substantially reduce or eliminate an unselected data line disturb. In various embodiments, the thyristor memory cell can be structured with two control nodes and its cathode or anode coupled to a reference voltage node common to all thyristor memory cells in a memory array. Additional apparatuses and methods are disclosed.

Abstract translation: 装置和方法可以包括用于晶闸管存储单元的写入方案，其中施加到晶闸管存储单元的栅极的访问脉冲相对于数据脉冲被调整以将数据写入晶闸管存储单元。 一些写入方案可以显着地减少或消除未选择的数据线干扰。 在各种实施例中，晶闸管存储单元可以由两个控制节点构成，其阴极或阳极耦合到存储器阵列中所有可控硅存储器单元公共的参考电压节点。 公开了附加的装置和方法。

公开(公告)号：US08324656B1

公开(公告)日：2012-12-04

申请号：US13175676

申请日：2011-07-01

Applicant: Rajesh N. Gupta ,  Marc Laurent Tarabbia ,  Kevin J. Yang

Inventor： Rajesh N. Gupta ,  Marc Laurent Tarabbia ,  Kevin J. Yang

IPC: H01L29/74

CPC classification number: H01L27/1203 ,  G11C11/39 ,  H01L27/1027 ,  H01L29/7436

Abstract: Embodiments of integrated circuits for mitigating against electrostatic coupling are described. In an embodiment, first gate dielectrics are respectively located over first active regions. First isolation regions are respectively located between the first active regions. Second gate dielectrics are respectively located over second active regions. Second isolation regions are respectively located between the second active regions. In an embodiment, the first active regions are approximately 20 to 80 percent shorter in height/thickness than the second active regions. In another embodiment, the first isolation regions extend above an uppermost surface of the first gate dielectrics while providing gaps between the first isolation regions and sidewalls of the first active regions for receipt of material used in formation of conductive lines. In yet another embodiment, active area stripes are narrower in width at p-base regions and n-base regions than at cathode regions and anode regions respectively thereof.

Abstract translation: 描述了用于减轻静电耦合的集成电路的实施例。 在一个实施例中，第一栅极电介质分别位于第一有源区上。 第一隔离区分别位于第一活性区之间。 第二栅极电介质分别位于第二有源区上。 第二隔离区域分别位于第二活性区域之间。 在一个实施例中，第一活性区域的高度/厚度比第二活性区域短约20至80％。 在另一个实施例中，第一隔离区域在第一栅极电介质的最上表面上方延伸，同时在第一隔离区域和第一有源区域的侧壁之间提供间隙，以便接收用于形成导电线路的材料。 在另一个实施例中，有源区条纹在p基区和n基区域的宽度分别窄于阴极区和阳极区。

公开(公告)号：US07554130B1

公开(公告)日：2009-06-30

申请号：US11361869

申请日：2006-02-23

Applicant: Scott Robins ,  Kevin J. Yang ,  Rajesh N. Gupta

Inventor： Scott Robins ,  Kevin J. Yang ,  Rajesh N. Gupta

IPC: H01L29/74

CPC classification number: H01L27/1027 ,  H01L29/7436

Abstract: An integrated circuit having memory, including thyristor-based memory cells, is described, where each of the thyristor-based memory cells includes a thyristor-based storage element and an access transistor. Where the thyristor-based storage element includes an anode region and a cathode region, a pair of the thyristor-based memory cells are commonly coupled via a bitline associated with the access transistor or via a reference voltage line coupled to the anode region. Bitline or anode regions are separated from one another by an isolation region. In another configuration, a bitline region has a locally implant-damaged region to inhibit charge transfer between the pair. In yet another configuration, a storage node contact or contacts respectively can extend over or are coupled to a storage node line extending over an isolation region. In this latter configuration, a source/drain region and the cathode region are separated from one another by an isolation region.

Abstract translation: 描述了一种具有存储器的集成电路，包括基于晶闸管的存储单元，其中每个基于晶闸管的存储单元包括基于晶闸管的存储元件和存取晶体管。 在基于晶闸管的存储元件包括阳极区域和阴极区域的情况下，一对基于晶闸管的存储单元通常经由与存取晶体管相关联的位线或经由耦合到阳极区域的参考电压线耦合。 位线或阳极区域通过隔离区域彼此分离。 在另一种配置中，位线区域具有局部注入损坏区域，以阻止该对之间的电荷转移。 在另一种配置中，存储节点接触点或触头分别可以延伸超过或耦合到在隔离区域上延伸的存储节点线。 在后一种配置中，源极/漏极区域和阴极区域通过隔离区域彼此分离。

公开(公告)号：US06201267B1

公开(公告)日：2001-03-13

申请号：US09260320

申请日：1999-03-01

Applicant: Rajesh N. Gupta ,  Michael Shur

Inventor： Rajesh N. Gupta ,  Michael Shur

IPC: H01L2710

CPC classification number: H01L27/11 ,  H01L27/092 ,  H01L27/1108 ,  H01L27/1203

Abstract: A complementary Field Effect Transistor includes a first transistor and a second transistor stacked on the first transistor. The angle between the source/drain pair for the first transistor and the source/drain pair for the second transistor is nonzero and other than 180 degrees (e.g., 90 degrees). In one embodiment, each transistor has its own gate, and the active regions for the transistors are separated and situated between the gates. In another embodiment, the active regions for the transistors share a single channel region. In still another embodiment, the transistors share a single gate. In yet another embodiment, the transistors share both a channel region and a gate.

Abstract translation: 互补场效应晶体管包括堆叠在第一晶体管上的第一晶体管和第二晶体管。 第一晶体管的源/漏对与第二晶体管的源极/漏极对之间的角度为非零，而不是180度（例如，90度）。 在一个实施例中，每个晶体管具有其自己的栅极，并且用于晶体管的有源区域被分离并位于栅极之间。 在另一个实施例中，晶体管的有源区共享单个沟道区。 在又一个实施例中，晶体管共享一个栅极。 在另一个实施例中，晶体管共享沟道区和栅极。

公开(公告)号：US08952418B2

公开(公告)日：2015-02-10

申请号：US13037642

申请日：2011-03-01

Applicant: Rajesh N. Gupta ,  Farid Nemati ,  Scott T. Robins

Inventor： Rajesh N. Gupta ,  Farid Nemati ,  Scott T. Robins

IPC: H01L29/74 ,  H01L29/73 ,  H01L27/102 ,  H01L29/735 ,  H01L27/108 ,  H01L29/78

CPC classification number: H01L27/1026 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/8229 ,  H01L27/1023 ,  H01L27/1024 ,  H01L27/10802 ,  H01L29/1608 ,  H01L29/73 ,  H01L29/732 ,  H01L29/735 ,  H01L29/7391 ,  H01L29/7841 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments include gated bipolar junction transistors. The transistors may include a base region between a collector region and an emitter region; with a B-C junction being at an interface of the base region and the collector region, and with a B-E junction being at an interface of the base region and the emitter region. The transistors may include material having a bandgap of at least 1.2 eV within one or more of the base, emitter and collector regions. The gated transistors may include a gate along the base region and spaced from the base region by dielectric material, with the gate not overlapping either the B-C junction or the B-E junction. Some embodiments include memory arrays containing gated bipolar junction transistors. Some embodiments include methods of forming gated bipolar junction transistors.

Abstract translation: 一些实施例包括门极双极结型晶体管。 晶体管可以包括在集电极区域和发射极区域之间的基极区域; 其中B-C结位于基极区和集电极区的界面处，并且B-E结位于基极区和发射极区的界面处。 晶体管可以包括在一个或多个基极，发射极和集电极区内具有至少1.2eV的带隙的材料。 栅极晶体管可以包括沿着基极区域的栅极并且通过电介质材料与基极区域间隔开，栅极不与B-C结或B-E结重叠。 一些实施例包括包含门极双极结型晶体管的存储器阵列。 一些实施例包括形成门控双极结型晶体管的方法。

公开(公告)号：US20120228629A1

公开(公告)日：2012-09-13

申请号：US13043295

申请日：2011-03-08

Applicant: Farid Nemati ,  Scott T. Robins ,  Rajesh N. Gupta

Inventor： Farid Nemati ,  Scott T. Robins ,  Rajesh N. Gupta

IPC: H01L29/74 ,  H01L21/8229 ,  H01L21/22

CPC classification number: G11C11/39 ,  H01L21/28008 ,  H01L21/30604 ,  H01L21/76224 ,  H01L27/0817 ,  H01L27/1027 ,  H01L29/7455 ,  H01L29/749

Abstract: Some embodiments include thyristors having first and second electrode regions, first and second base regions, and material having a bandgap of at least 1.2 eV in at least one of the regions. The first base region is between the first electrode region and the second base region, and the second base region is between the second electrode region and the first base region. The first base region interfaces with the first electrode region at a first junction, and interfaces with the second base region at a second junction. The second base region interfaces with the second electrode region at a third junction. A gate is along the first base region, and in some embodiments does not overlap either of the first and second junctions. Some embodiments include methods of programming thyristors, and some embodiments include methods of forming thyristors.

Abstract translation: 一些实施例包括具有第一和第二电极区域，第一和第二基极区域以及在至少一个区域中具有至少1.2eV的带隙的材料的晶闸管。 第一基极区域在第一电极区域和第二基极区域之间，第二基极区域在第二电极区域和第一基极区域之间。 第一基区在第一结处与第一电极区相接，并且在第二结处与第二基区交界。 第二基极区域在第三结区与第二电极区域相接合。 栅极沿着第一基极区域，并且在一些实施例中不与第一和第二结点重叠。 一些实施例包括编程晶闸管的方法，并且一些实施例包括形成晶闸管的方法。