公开(公告)号：US20120092862A1

公开(公告)日：2012-04-19

申请号：US12903208

申请日：2010-10-13

Applicant: SHIH-JEN CHUANG ,  Han-Chi Chang

Inventor： SHIH-JEN CHUANG ,  Han-Chi Chang

IPC: F21V9/00

CPC classification number: F21K9/00 ,  F21Y2105/10 ,  F21Y2105/12 ,  F21Y2113/13 ,  F21Y2115/10

Abstract: Disclosed is a structure of light-emitting diode (LED) having high color rendering index, including a substrate on which at least one light emission element, at least one red light emission element, and at least one green light emission element are mounted. The light emission element emits blue light that is also applied to excite a fluorescent powder coated outside the light emission element to generate white light, which when mixed with red and green lights from the red and green light emission elements, form a light source of improved color rendering property. With the addition of the red and green light emission elements, the light projecting from the LED structure provides a color performance close to the natural light, allowing for perfect reproduction of the original color of an object and thereby improving conformableness and coordination of human perception without causing any lose of color genuineness of an object.

Abstract translation: 公开了具有高显色指数的发光二极管（LED）的结构，包括其上安装有至少一个发光元件，至少一个红色发光元件和至少一个绿色发光元件的基板。 发光元件发射蓝光，其也被施加以激发涂覆在发光元件外部的荧光粉，以产生白光，当与来自红色和绿色发光元件的红色和绿色光混合时，形成改进的光源 显色性能。 通过添加红色和绿色发光元件，从LED结构突出的光提供了接近自然光的颜色性能，从而可以完美地再现对象的原始颜色，从而提高人类感知的一致性和协调性，而无需 导致物体的色彩真实性丧失。

公开(公告)号：US20120091894A1

公开(公告)日：2012-04-19

申请号：US12903218

申请日：2010-10-13

Applicant: SHIH-JEN CHUANG ,  Han-Chi Chang ,  Chun-Yi Tsai

Inventor： SHIH-JEN CHUANG ,  Han-Chi Chang ,  Chun-Yi Tsai

IPC: F21V29/00 ,  H05B37/02

CPC classification number: H05B33/0803 ,  F21K9/23 ,  F21K9/238 ,  F21V17/002 ,  F21V23/006 ,  F21V23/02 ,  F21Y2105/10 ,  F21Y2115/10 ,  H05B33/0815 ,  H05B33/0845 ,  H05B33/089

Abstract: An LED (Light-Emitting Diode) driving device is electrically connectable with an alternating current (AC) power supply and includes an electronic converter received in the driving device and a first connector, which is formed on an end of the driving device to connect with the AC power supply and in electrical connection with the electronic converter, and a second connector, which is formed on another end of the driving device for connection with an LED lighting module. When the first connector is set in electrical connection with the AC power supply, the above arrangement allows for conversion of electrical current and voltage to those applicable to an LED lighting module within 10 W rating.

Abstract translation: LED（发光二极管）驱动装置可与交流（AC）电源电连接，并且包括容纳在驱动装置中的电子转换器和形成在驱动装置的一端上的第一连接器， AC电源并与电子转换器电连接，以及第二连接器，其形成在用于与LED照明模块连接的驱动装置的另一端上。 当第一连接器与AC电源电连接时，上述布置允许将电流和电压转换成适用于10W额定值内的LED照明模块。

公开(公告)号：US07863933B2

公开(公告)日：2011-01-04

申请号：US12117163

申请日：2008-05-08

Applicant: Shih-Jen Chuang

Inventor： Shih-Jen Chuang

IPC: H03K19/0175

CPC classification number: G06F13/4072

Abstract: The present invention discloses a tri-state I/O port. The tri-state I/O port comprises a tri-state logic block, a weak buffer and a delay block. The input terminals of the tri-state logic block are connected to data and OE (output enable) signals. When OE signal is enabled, the output terminal of the tri-state I/O block is pulled high when the data is high while the output terminal is pulled low when the data is low. The input terminal and the output terminal of the weak buffer are connected to the output terminal of the tri-state logic block. And the input terminal of the delay block is connected to the output terminal of the tri-state logic block while the output terminal of the delay block is fed back to the tri-state logic block. When the output terminal of the tri-state logic block is low to high/high to low, the weak buffer is active and maintains the output terminal of the tri-state logic block weak high/low while the delay block turns off the pull high/low function of the tri-state logic block.

Abstract translation: 本发明公开了一种三态I / O端口。 三态I / O端口包括三态逻辑块，弱缓冲器和延迟块。 三态逻辑块的输入端连接到数据和OE（输出使能）信号。 当OE信号使能时，数据为高电平时，三态I / O模块的输出端子拉高，而数据为低电平时，输出端子拉低。 弱缓冲器的输入端子和输出端子连接到三态逻辑块的输出端子。 并且延迟块的输入端子连接到三态逻辑块的输出端，而延迟块的输出端反馈到三态逻辑块。 当三态逻辑块的输出端子由低到高/高到低时，弱缓冲器有效，并且三态逻辑块的输出端子在高电平/低电平时保持低电平，而延迟模块关闭拉高 /三态逻辑块的低功能。

公开(公告)号：US07547960B2

公开(公告)日：2009-06-16

申请号：US11510661

申请日：2006-08-28

Applicant: Ming-Jing Lee ,  Shih-Jen Chuang ,  Chih-Hung Hsu ,  Chin-Chia Hsu

Inventor： Ming-Jing Lee ,  Shih-Jen Chuang ,  Chih-Hung Hsu ,  Chin-Chia Hsu

IPC: H01L23/495

CPC classification number: H01L31/12 ,  H01L25/167 ,  H01L31/02002 ,  H01L33/62 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure of a lead-frame matrix of photoelectron devices is provided. The lead-frame matrix is used to fabricate a first lead-frame array and a second lead-frame array. In the structure of the lead-frame matrix of the photoelectron devices, pins of the first lead-frame array and pins of the second lead-frame array are alternatively inserted.

Abstract translation: 提供了光电子器件的引线框矩阵的结构。 引线框矩阵用于制造第一引线框架阵列和第二引线框架阵列。 在光电子器件的引线框矩阵的结构中，第一引线框架阵列的引脚和第二引线框架阵列的引脚交替插入。

公开(公告)号：US20090150734A1

公开(公告)日：2009-06-11

申请号：US12117163

申请日：2008-05-08

Applicant: Shih-Jen CHUANG

Inventor： Shih-Jen CHUANG

IPC: G01R31/28

CPC classification number: G06F13/4072

Abstract: The present invention discloses a tri-state I/O port. The tri-state I/O port comprises a tri-state logic block, a weak buffer and a delay block. The input terminals of the tri-state logic block are connected to data and OE (output enable) signals. When OE signal is enabled, the output terminal of the tri-state I/O block is pulled high when the data is high while the output terminal is pulled low when the data is low. The input terminal and the output terminal of the weak buffer are connected to the output terminal of the tri-state logic block. And the input terminal of the delay block is connected to the output terminal of the tri-state logic block while the output terminal of the delay block is fed back to the tri-state logic block. When the output terminal of the tri-state logic block is low to high/high to low, the weak buffer is active and maintains the output terminal of the tri-state logic block weak high/low while the delay block turns off the pull high/low function of the tri-state logic block.

Abstract translation: 本发明公开了一种三态I / O端口。 三态I / O端口包括三态逻辑块，弱缓冲器和延迟块。 三态逻辑块的输入端连接到数据和OE（输出使能）信号。 当OE信号使能时，数据为高电平时，三态I / O模块的输出端子拉高，而数据为低电平时，输出端子拉低。 弱缓冲器的输入端子和输出端子连接到三态逻辑块的输出端子。 并且延迟块的输入端子连接到三态逻辑块的输出端，而延迟块的输出端反馈到三态逻辑块。 当三态逻辑块的输出端子由低到高/高到低时，弱缓冲器有效，并且三态逻辑块的输出端子在高电平/低电平时保持低电平，而延迟模块关闭拉高 /三态逻辑块的低功能。

公开(公告)号：US20090135618A1

公开(公告)日：2009-05-28

申请号：US12046895

申请日：2008-03-12

Applicant: Abram CHANG ,  Shih-Jen Chuang

Inventor： Abram CHANG ,  Shih-Jen Chuang

IPC: F21V21/28 ,  B60Q1/00

CPC classification number: B60Q1/2696 ,  H05B33/0821 ,  H05B33/0887 ,  Y02B20/341

Abstract: A circuit apparatus of an LED vehicle lamp is disclosed. The circuit apparatus includes an input unit, an LED unit and a current limiting unit. The LED unit includes at least one light-emitting device. Each light-emitting device includes at least one LED and a protection device. The protection device and each one LED are connected in parallel. The circuit apparatus of an LED vehicle lamp protects the element of the LEDs from being damaged, increases traveling safety and simplifies maintenance.

Abstract translation: 公开了一种LED车灯的电路装置。 电路装置包括输入单元，LED单元和限流单元。 LED单元包括至少一个发光装置。 每个发光装置包括至少一个LED和保护装置。 保护装置和每个LED并联连接。 LED车灯的电路装置保护LED的元件免受损坏，提高行驶安全性并简化维护。

公开(公告)号：US20070257342A1

公开(公告)日：2007-11-08

申请号：US11510716

申请日：2006-08-28

Applicant: Ming-Jing Lee ,  Shih-Jen Chuang ,  Chih-Hung Hsu ,  Yi-Hu Chao

Inventor： Ming-Jing Lee ,  Shih-Jen Chuang ,  Chih-Hung Hsu ,  Yi-Hu Chao

IPC: H01L21/00

CPC classification number: H01L25/167 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of manufacturing photo couplers is provided. At first, a receiver lead-frame array is cut from a lead-frame matrix having a transmitter lead-frame array and the receiver lead-frame array. Then, the receiver lead-frame array is overturned and placed on the lead-frame matrix to allow light-receiver elements on the receiver lead-frame array to face light-emitting elements on the transmitter lead-frame array of the lead-frame matrix. Finally, the receiver lead-frame array and the lead-frame matrix are connected.

Abstract translation: 提供一种制造光耦合器的方法。 首先，从具有发射器引线框阵列和接收器引线框架阵列的引线框矩阵切割接收器引线框架阵列。 然后，接收器引线框架阵列被翻转并放置在引线框矩阵上，以使接收器引线框架阵列上的光接收器元件面对引线框矩阵的发射器引线框架阵列上的发光元件 。 最后，连接接收器引线框架阵列和引线框矩阵。

公开(公告)号：US20060277337A1

公开(公告)日：2006-12-07

申请号：US11235807

申请日：2005-09-26

Applicant: Shih-Jen Chuang ,  Chih-Fu Tsai ,  Shu-Min Liu

Inventor： Shih-Jen Chuang ,  Chih-Fu Tsai ,  Shu-Min Liu

IPC: G06F13/38 ,  G06F13/12

CPC classification number: G06F3/0661 ,  G06F3/0607 ,  G06F3/0658 ,  G06F3/0679

Abstract: A conversion interface of memory device is provided for converting a current operating command of a user's software program to an operating command capable of being executed by the memory device. The conversion interface includes a command decoding module and a command generating module. The command decoding module receives the operating command of the user's software program and decodes the operating command to a decoding command, such that the command generating module generates the operating command capable of being executed by the memory device according to the decoding command. This can realize compatibility between a current software program and a new type of memory device, thereby effectively reducing the design costs and product development cycle and providing great flexibility in design.

Abstract translation: 提供存储器件的转换接口，用于将用户软件程序的当前操作命令转换为能够由存储器件执行的操作命令。 转换接口包括命令解码模块和命令生成模块。 命令解码模块接收用户软件程序的操作命令，并将操作命令解码为解码命令，使得命令生成模块根据解码命令生成能够由存储器件执行的操作命令。 这可以实现当前软件程序与新型存储器件的兼容性，从而有效地降低了设计成本和产品开发周期，并提供了很大的设计灵活性。

公开(公告)号：US20050050280A1

公开(公告)日：2005-03-03

申请号：US10830592

申请日：2004-04-22

Applicant: Chang-Cheng Yap ,  Shih-Jen Chuang

Inventor： Chang-Cheng Yap ,  Shih-Jen Chuang

IPC: G06F9/06 ,  G06F9/38 ,  G06F12/00

CPC classification number: G06F9/383 ,  G06F9/3802 ,  G06F9/3832

Abstract: A data accessing method and a system for use with the same are provided. A processing unit reads a command from a memory unit and decodes the command. Then, the processing unit determines if the command requires pre-fetching of data that are not stored in a cache or a buffer unit; if yes, the processing unit sends a fetching request to the memory unit according to addresses of data to be fetched and pre-fetched. Moreover, the processing unit reads the data to be fetched from the memory unit and stores the data to be pre-fetched in the buffer unit. Thereby, the above method and system can achieve data pre-fetching accurately.

Abstract translation: 提供了一种数据存取方法及其使用的系统。 处理单元从存储器单元读取命令并解码该命令。 然后，处理单元确定该命令是否需要预取未存储在高速缓存或缓冲单元中的数据; 如果是，则处理单元根据要获取和预取的数据的地址向存储器单元发送取出请求。 此外，处理单元从存储器单元读取要获取的数据，并将要预取的数据存储在缓冲单元中。 因此，上述方法和系统可以准确地实现数据预取。

公开(公告)号：US5761718A

公开(公告)日：1998-06-02

申请号：US705738

申请日：1996-08-30

Applicant: Yung Cheng Lin ,  Shih Jen Chuang

Inventor： Yung Cheng Lin ,  Shih Jen Chuang

IPC: G06F9/38 ,  G06F12/08

CPC classification number: G06F12/0862 ,  G06F9/383 ,  G06F2212/6026

Abstract: An algorithm for conditionally pre-fetching data for DRAM access is disclosed. A similar pattern of performing successive block reads of DRAM data in the execution of several types of instructions in a computer system is determined by analyzing CPU signals. These instructions repeatedly read blocks of data from a local memory area. Additional writes to memory or an input/output port may intervene between the repeated block reads. By using the pattern as a condition for pre-fetching data from DRAM into a high speed memory buffer of a memory controller, consecutive memory reads can be completed with zero wait state. The penalty incurred by unconditional pre-fetching of DRAM data is minimized. The conditional pre-fetching mechanism is applicable to other computer peripheral devices.

Abstract translation: 公开了一种用于有条件地预取DRAM访问数据的算法。 通过分析CPU信号来确定执行计算机系统中的几种类型的指令的DRAM数据的连续块读取的类似模式。 这些指令重复从本地存储区读取数据块。 对存储器或输入/输出端口的额外写入可能会在重复的块读取之间进行干预。 通过使用该模式作为将数据从DRAM预取到存储器控制器的高速存储器缓冲器的条件，可以以零等待状态完成连续存储器读取。 无条件预取DRAM数据造成的惩罚最小化。 条件预取机制适用于其他计算机外围设备。