公开(公告)号：US20080184066A1

公开(公告)日：2008-07-31

申请号：US11751091

申请日：2007-05-21

Applicant: Shih-Jen Chuang ,  Chang-Cheng Yap ,  Bo-Yuan Shih

Inventor： Shih-Jen Chuang ,  Chang-Cheng Yap ,  Bo-Yuan Shih

IPC: G06F11/00

CPC classification number: G06F11/2028 ,  G06F11/1645 ,  G06F11/2051

Abstract: A redundant system comprising at least two hosts is provided. The redundant system randomly selects one active host under normal operating conditions, and sets the other hosts on stand-by. The active host controls the other hosts and peripheral devices connecting thereto through buses.

Abstract translation: 提供了包括至少两个主机的冗余系统。 冗余系统在正常工作条件下随机选择一台活动主机，并将其他主机置于待机状态。 主动主机通过总线控制与其连接的其他主机和外围设备。

公开(公告)号：US20110191513A1

公开(公告)日：2011-08-04

申请号：US12900031

申请日：2010-10-07

Applicant: Chang-Cheng YAP ,  Ching-Yun CHENG

Inventor： Chang-Cheng YAP ,  Ching-Yun CHENG

IPC: G06F13/24

CPC classification number: G06F13/24

Abstract: An interrupt control system comprises: a central processing unit (CPU); a peripheral device; an interrupt controller, and an interrupt preprocessing circuit. The peripheral device optionally issues an interrupt request, and the interrupt controller generates and outputs a first interrupt request signal in response to the interrupt request. The interrupt preprocessing circuit generates and outputs two first interrupt acknowledgement signals to the interrupt controller in response to the first interrupt request signal. An interrupt vector is generated and outputted by the interrupt controller in response to the two first interrupt acknowledgement signals, and the interrupt vector is transmitted to the CPU through the interrupt preprocessing circuit.

Abstract translation: 中央控制系统包括：中央处理单元（CPU）; 外围设备; 中断控制器和中断预处理电路。 外围设备可选地发出中断请求，并且中断控制器响应于中断请求产生并输出第一个中断请求信号。 中断预处理电路响应于第一个中断请求信号产生并向中断控制器输出两个第一中断确认信号。 中断控制器响应于两个第一个中断确认信号产生并输出一个中断向量，并且中断向量通过中断预处理电路发送到CPU。

公开(公告)号：US20110246838A1

公开(公告)日：2011-10-06

申请号：US12968565

申请日：2010-12-15

Applicant: Chun-Jieh Huang ,  Huan-Chau Lin ,  Chang Cheng Yap

Inventor： Chun-Jieh Huang ,  Huan-Chau Lin ,  Chang Cheng Yap

IPC: G06F11/00

CPC classification number: G06F11/2236

Abstract: A device for use in inspecting a CPU and a method thereof are provided. The device comprises a receiving interface and a processor. The receiving interface receives a first data stream from the CPU when the CPU executes a reference hardware inspection program in a first time interval, and receives a second data stream from the CPU when the CPU executes the reference hardware inspection program in a second time interval. The processor sets the first data stream as a good log, and sets the second data stream as an erroneous log. The processor compares the good log and the erroneous log to determine a segment of the erroneous log as an erroneous range, and determine a defect of the CPU according to the erroneous range.

Abstract translation: 提供了一种用于检查CPU的装置及其方法。 该设备包括接收接口和处理器。 当CPU在第一时间间隔内执行参考硬件检查程序时，接收接口从CPU接收第一数据流，并且当CPU在第二时间间隔内执行参考硬件检查程序时，从CPU接收第二数据流。 处理器将第一个数据流设置为良好的日志，并将第二个数据流设置为错误日志。 处理器比较好的日志和错误日志来确定错误日志的一个段作为错误的范围，并根据错误的范围确定CPU的缺陷。

公开(公告)号：US20070271407A1

公开(公告)日：2007-11-22

申请号：US11834718

申请日：2007-08-07

Applicant: Chang-Cheng Yap ,  Shih-Jen Chuang

Inventor： Chang-Cheng Yap ,  Shih-Jen Chuang

IPC: G06F13/36

CPC classification number: G06F9/383 ,  G06F9/3802 ,  G06F9/3832

Abstract: A data accessing method executed by a processing unit, the method comprising the steps of: (a) decoding an instruction; (b) checking whether the instruction has to be repeated M times to read data with successive addresses in a main memory, wherein the number M is stored in a count register of the processing unit; (c) if the step (b) is true, getting a data from a cache, a pre-fetch buffer, or the main memory, and then decreasing M by one; (d) if M is zero, terminating the data accessing method; (e) determining and pre-fetching data by comparing M to the number of unread data stored in the cache and the pre-fetch buffer; and (f) getting the next data from the cache or the pre-fetch buffer, decreasing M by one, and then returning to step (d).

Abstract translation: 一种由处理单元执行的数据访问方法，所述方法包括以下步骤：（a）解码指令; （b）检查指令是否必须重复M次以便在主存储器中用连续地址读取数据，其中数量M存储在处理单元的计数寄存器中; （c）如果步骤（b）为真，从高速缓存，预取缓冲器或主存储器获取数据，然后将M减1; （d）如果M为零，则终止数据访问方法; （e）通过将M与存储在高速缓存和预取缓冲器中的未读数据的数量进行比较来确定和预取数据; 和（f）从高速缓存或预取缓冲器获取下一个数据，将M减1，然后返回步骤（d）。

公开(公告)号：US20060136651A1

公开(公告)日：2006-06-22

申请号：US11088027

申请日：2005-03-22

Applicant: Chang-Cheng Yap ,  Chih-Fu Tsai ,  Chien-Min Hsieh

Inventor： Chang-Cheng Yap ,  Chih-Fu Tsai ,  Chien-Min Hsieh

IPC: G06F13/00

CPC classification number: G06F13/4063

Abstract: A selectively-switchable bus connecting device is proposed, which is designed for use in conjunction with a chip device for connecting the multiple signal lines of the chip device's internal bus in a user-specified mapping manner to the multiple signal lines of a socket on an external circuit board. This feature allows chip devices of the same type to be usable for mounting on different types of circuit boards having different socket signal line arrangements, with the benefits of flexible arrangements and cost-effective design and manufacture of circuit boards with chip devices.

Abstract translation: 提出了一种可选择切换的总线连接装置，其被设计为与芯片装置结合使用，用于以用户指定的映射方式将芯片装置的内部总线的多条信号线连接到插座的多条信号线上 外部电路板。 该特征允许相同类型的芯片器件可用于安装在具有不同插座信号线布置的不同类型的电路板上，具有柔性布置和成本有效地设计和制造具有芯片器件的电路板的优点。

公开(公告)号：US20050125596A1

公开(公告)日：2005-06-09

申请号：US10729361

申请日：2003-12-04

Applicant: Chang-Cheng Yap

Inventor： Chang-Cheng Yap

IPC: G06F12/08 ,  G06F13/42 ,  G11C7/10 ,  G11C11/4096

CPC classification number: G06F13/4243 ,  G11C7/1027 ,  G11C11/4096

Abstract: An access control unit and method is proposed for use with an SDRAM (Synchronous Dynamic Random-Access Memory) device to control each round of burst-transfer type of access operation on the SDRAM device. The proposed access control unit and method is characterized by that the column-address strobe signal involved in each round of the burst-transfer access operation is continuously set at active state for a period of clock pulses equal in number to the specified burst length of the burst-transfer access operation, rather than just for a period of one pulse. This feature allows external circuitry to arbitrarily change the burst length, and also allows no use of burst-stop command or a precharge-interrupt method to stop each round of the burst-transfer access operation, allowing the access control logic circuit architecture to be more simplified than the prior art.

Abstract translation: 提出了一种与SDRAM（同步动态随机存取存储器）装置一起使用的访问控制单元和方法，以在SDRAM设备上控制每一轮的突发传送类型的访问操作。 所提出的访问控制单元和方法的特征在于，在每一次突发传送访问操作中涉及的列地址选通信号被连续地设置在激活状态，时钟脉冲的周期等于数目的指定突发长度 突发传输接入操作，而不仅仅是一个脉冲的周期。 该特征允许外部电路任意地改变突发长度，并且也不允许使用突发停止命令或预充电中断方法来停止每一个突发传送访问操作，允许访问控制逻辑电路架构更多 比现有技术简化。

公开(公告)号：US08489927B2

公开(公告)日：2013-07-16

申请号：US12968565

申请日：2010-12-15

Applicant: Chun-Jieh Huang ,  Huan-Chau Lin ,  Chang Cheng Yap

Inventor： Chun-Jieh Huang ,  Huan-Chau Lin ,  Chang Cheng Yap

IPC: G06F11/00

CPC classification number: G06F11/2236

Abstract: A device for use in inspecting a CPU and a method thereof are provided. The device comprises a receiving interface and a processor. The receiving interface receives a first data stream from the CPU when the CPU executes a reference hardware inspection program in a first time interval, and receives a second data stream from the CPU when the CPU executes the reference hardware inspection program in a second time interval. The processor sets the first data stream as a good log, and sets the second data stream as an erroneous log. The processor compares the good log and the erroneous log to determine a segment of the erroneous log as an erroneous range, and determine a defect of the CPU according to the erroneous range.

Abstract translation: 提供了一种用于检查CPU的装置及其方法。 该设备包括接收接口和处理器。 当CPU在第一时间间隔内执行参考硬件检查程序时，接收接口从CPU接收第一数据流，并且当CPU在第二时间间隔内执行参考硬件检查程序时，从CPU接收第二数据流。 处理器将第一个数据流设置为良好的日志，并将第二个数据流设置为错误日志。 处理器比较好的日志和错误日志来确定错误日志的一个段作为错误的范围，并根据错误的范围确定CPU的缺陷。

公开(公告)号：US07103707B2

公开(公告)日：2006-09-05

申请号：US10729361

申请日：2003-12-04

Applicant: Chang-Cheng Yap

Inventor： Chang-Cheng Yap

IPC: G06F13/16

CPC classification number: G06F13/4243 ,  G11C7/1027 ,  G11C11/4096

Abstract: An access control unit and method is proposed for use with an SDRAM (Synchronous Dynamic Random-Access Memory) device to control each round of burst-transfer type of access operation on the SDRAM device. The proposed access control unit and method is characterized by that the column-address strobe signal involved in each round of the burst-transfer access operation is continuously set at active state for a period of clock pulses equal in number to the specified burst length of the burst-transfer access operation, rather than just for a period of one pulse. This feature allows external circuitry to arbitrarily change the burst length, and also allows no use of burst-stop command or a precharge-interrupt method to stop each round of the burst-transfer access operation, allowing the access control logic circuit architecture to be more simplified than the prior art.

Abstract translation: 提出了一种与SDRAM（同步动态随机存取存储器）装置一起使用的访问控制单元和方法，以在SDRAM设备上控制每一轮的突发传送类型的访问操作。 所提出的访问控制单元和方法的特征在于，在每一次突发传送访问操作中涉及的列地址选通信号被连续地设置在激活状态，时钟脉冲的周期等于数目的指定突发长度 突发传输接入操作，而不仅仅是一个脉冲的周期。 该特征允许外部电路任意地改变突发长度，并且也不允许使用突发停止命令或预充电中断方法来停止每一个突发传送访问操作，允许访问控制逻辑电路架构更多 比现有技术简化。

公开(公告)号：US20050050280A1

公开(公告)日：2005-03-03

申请号：US10830592

申请日：2004-04-22

Applicant: Chang-Cheng Yap ,  Shih-Jen Chuang

Inventor： Chang-Cheng Yap ,  Shih-Jen Chuang

IPC: G06F9/06 ,  G06F9/38 ,  G06F12/00

CPC classification number: G06F9/383 ,  G06F9/3802 ,  G06F9/3832

Abstract: A data accessing method and a system for use with the same are provided. A processing unit reads a command from a memory unit and decodes the command. Then, the processing unit determines if the command requires pre-fetching of data that are not stored in a cache or a buffer unit; if yes, the processing unit sends a fetching request to the memory unit according to addresses of data to be fetched and pre-fetched. Moreover, the processing unit reads the data to be fetched from the memory unit and stores the data to be pre-fetched in the buffer unit. Thereby, the above method and system can achieve data pre-fetching accurately.

Abstract translation: 提供了一种数据存取方法及其使用的系统。 处理单元从存储器单元读取命令并解码该命令。 然后，处理单元确定该命令是否需要预取未存储在高速缓存或缓冲单元中的数据; 如果是，则处理单元根据要获取和预取的数据的地址向存储器单元发送取出请求。 此外，处理单元从存储器单元读取要获取的数据，并将要预取的数据存储在缓冲单元中。 因此，上述方法和系统可以准确地实现数据预取。