公开(公告)号：US5555230A

公开(公告)日：1996-09-10

申请号：US475838

申请日：1995-06-07

Applicant: Motokazu Kashida ,  Hidenori Hoshi ,  Kenichi Nagasawa ,  Shinichi Yamashita

Inventor： Motokazu Kashida ,  Hidenori Hoshi ,  Kenichi Nagasawa ,  Shinichi Yamashita

IPC: G11B15/467 ,  G11B20/10 ,  G11B20/12 ,  G11B20/18 ,  G11B27/30 ,  H04N5/7826 ,  H04N9/797 ,  H04N9/877 ,  H04N9/888

CPC classification number: H04N5/78266 ,  G11B15/4678 ,  G11B20/10 ,  G11B20/10527 ,  G11B20/1833 ,  G11B27/3009 ,  G11B27/3027 ,  H04N9/7973 ,  H04N9/877 ,  H04N9/888 ,  G11B20/1208 ,  G11B2020/10592 ,  G11B2220/90

Abstract: An apparatus for reproducing digital information from a recording medium having a plurality of parallel tracks and digital information recorded thereon as n-channel (n being an integer greater than or equal to 2) digital signals. The n-channel digital signals are reproduced by n-reproducing heads. The digital information contained in the reproduced signals is stored in a storage device. Discriminating data is obtained for determining which of the n-channel digital signals reproduced correspond to the reproducing heads. The timing of an access device, accessing the storage device for performing a predetermined processing of the digital signals stored in the storage device relative to the reproducing timing of the digital information reproduced by the n reproducing heads, is controlled in accordance with the discrimination data.

Abstract translation: 一种用于从具有多个并行轨道和其上记录的数字信息的记录介质再现数字信息的装置，其中n信道（n是大于或等于2的整数）数字信号。 n路数字信号由n个再现头再现。 包含在再现信号中的数字信息被存储在存储装置中。 获得鉴别数据，用于确定所再现的n路数字信号中的哪一个对应于再现头。 根据鉴别数据控制存取装置的访问存储装置，用于对存储在存储装置中的数字信号进行预定处理，相对于由n个再现头再现的数字信息的再现定时。

公开(公告)号：US5481518A

公开(公告)日：1996-01-02

申请号：US307047

申请日：1994-09-16

Applicant: Motokazu Kashida ,  Hidenori Hoshi ,  Kenichi Nagasawa ,  Shinichi Yamashita

Inventor： Motokazu Kashida ,  Hidenori Hoshi ,  Kenichi Nagasawa ,  Shinichi Yamashita

IPC: G11B15/467 ,  G11B20/10 ,  G11B20/12 ,  G11B20/18 ,  G11B27/30 ,  H04N5/7826 ,  H04N9/797 ,  H04N9/877 ,  H04N9/888

CPC classification number: H04N5/78266 ,  G11B15/4678 ,  G11B20/10 ,  G11B20/10527 ,  G11B20/1833 ,  G11B27/3009 ,  G11B27/3027 ,  H04N9/7973 ,  H04N9/877 ,  H04N9/888 ,  G11B20/1208 ,  G11B2020/10592 ,  G11B2220/90

Abstract: An apparatus for reproducing digital information from a recording medium having a plurality of parallel tracks and digital information recorded thereon as n-channel (n being an integer greater than or equal to 2) digital signals. The n-channel digital signals are reproduced by n-reproducing heads. The digital information contained in the reproduced signals is stored in a storage device. Discriminating data is obtained for determining which of the n-channel digital signals reproduced correspond to the reproducing heads. The timing of an access device, accessing the storage device for performing a predetermined processing of the digital signals stored in the storage device relative to the reproducing timing of the digital information reproduced by the n reproducing heads, is controlled in accordance with the discrimination data.

公开(公告)号：US5400148A

公开(公告)日：1995-03-21

申请号：US273629

申请日：1994-07-12

Applicant: Motokazu Kashida ,  Shinichi Yamashita

Inventor： Motokazu Kashida ,  Shinichi Yamashita

IPC: H04N9/804 ,  H04N5/7824 ,  H04N5/95 ,  H04N9/80 ,  H04N9/808 ,  H04N9/83 ,  H04N9/89 ,  H04N5/76 ,  H04N9/79

CPC classification number: H04N9/831 ,  H04N5/7824

Abstract: A video signal processing apparatus for processing a video signal includes a plurality of series-connected signal processing circuits. A plurality of timing control circuits for respectively controlling the plurality of signal processing circuits in accordance with a reference signal are provided. At least one of the plurality of timing control circuits inputs a timing signal conforming to the reference signal, and delays the passage of the timing signal therethrough by a time interval corresponding to a delay time of the video signal generated by the corresponding signal processing circuit and outputs a delayed timing signal. Consequently, it is possible to minimize a change in the timing control circuits, that is, a change in the overall apparatus, caused by the partial change in the design of the signal processing circuits.

Abstract translation: 用于处理视频信号的视频信号处理装置包括多个串联连接的信号处理电路。 提供了用于分别根据参考信号控制多个信号处理电路的多个定时控制电路。 所述多个定时控制电路中的至少一个输入符合所述参考信号的定时信号，并且延迟所述定时信号通过其相应于由所述相应信号处理电路产生的视频信号的延迟时间的时间间隔，以及 输出延迟定时信号。 因此，可以最小化定时控制电路的变化，即由信号处理电路的设计的部分变化引起的整个装置的变化。

公开(公告)号：US5303245A

公开(公告)日：1994-04-12

申请号：US666608

申请日：1991-03-08

Applicant: Akihiro Shikakura ,  Shinichi Yamashita

Inventor： Akihiro Shikakura ,  Shinichi Yamashita

IPC: H03M13/00 ,  H03M13/09 ,  G06F11/10

CPC classification number: H03M13/09

Abstract: In an information signal processing arrangement, an information signal, to which an error detecting code has been added and a part of which other than the error detecting code has been set to a code indicating a predetermined value, is received. Error detection capability is increased by detecting an error in the information signal according to the error detecting code added to the received information signal, and detecting whether or not the part of the information signal set to the predetermined value has changed.

Abstract translation: 在信息信号处理装置中，接收已经添加了检错码的信息信号和除了检错码以外的其中一部分的信息信号已被设置成表示预定值的码。 通过根据添加到接收到的信息信号中的检错码检测信息信号中的错误，并检测设定为预定值的信息信号的部分是否已经改变来增加错误检测能力。

公开(公告)号：US5124853A

公开(公告)日：1992-06-23

申请号：US600143

申请日：1990-10-17

Applicant: Motokazu Kashida ,  Makoto Shimokoriyama ,  Shinichi Yamashita ,  Susumu Kozuki ,  Koji Takahashi

Inventor： Motokazu Kashida ,  Makoto Shimokoriyama ,  Shinichi Yamashita ,  Susumu Kozuki ,  Koji Takahashi

IPC: G11B5/592 ,  G11B15/467

CPC classification number: G11B15/4678 ,  G11B5/5922 ,  G11B5/00865

Abstract: In an information signal recording apparatus having an m (m.gtoreq.2) number of heads arranged to record, in many parallel tracks on a recording medium, information signals of the m number of channels by simultaneously tracing the surface of the medium while simultaneously forming thereby the m number of tracks, pilot signals of an n number of kinds are recorded in rotation along with the information signals of the m number of channels in such a way as to recur in a cycle of an (n.times.m) number of tracks.

Abstract translation: 在具有m（m> / = 2）个头的信息信号记录装置中，其布置成在记录介质上的多个并行轨道中记录m个通道的信息信号，同时同时跟踪介质的表面 由此形成m个磁道，n个类型的导频信号与m个信道数的信息信号一起被旋转地记录，以便以（n×m）个磁道的周期再现。

公开(公告)号：US4976998A

公开(公告)日：1990-12-11

申请号：US321738

申请日：1989-03-10

Applicant: Yasumasa Morimitu ,  Shinichi Yamashita

Inventor： Yasumasa Morimitu ,  Shinichi Yamashita

IPC: B05C3/10 ,  B05C3/20 ,  B05D1/18 ,  B05D7/00 ,  B60T13/567

CPC classification number: B60T13/567 ,  B05C3/20 ,  B05D1/18 ,  B05D1/002

Abstract: A method and apparatus for providing to an anti-rust treatment a peripheral portion a shell such as is associated with a brake booster and which comprises a pair of cylindrical members disposed in abutting relationship with each other and fastened together by a staking operation which occurs by applying a shearing action to the periphery of the abutting members at a plurality of locations. The substantially cylindrical shell is held at an angle with respect to the horizontal, and then driven for rotation. A vehicle containing an anti-rust paint is disposed below the rotating shell, and the shell is positioned so that its axis of rotation does not intersect the vessel. As the shell rotates, the shear-staked peripheral portion of the shell is successively brought into dipping relationship with the paint.

Abstract translation: 一种用于对周边部分进行防锈处理的方法和装置，所述外壳包括与制动助力器相关联的外壳，所述外壳包括一对彼此邻接关系设置的圆柱形构件，并通过由 在多个位置处对邻接构件的周边施加剪切动作。 基本上圆柱形的壳体相对于水平面保持一定角度，然后被驱动旋转。 含有防锈油漆的车辆设置在旋转壳体的下方，壳体定位成使其旋转轴线不与容器相交。 随着壳旋转，壳体的剪切桩周边部分与涂料相连接。

公开(公告)号：US4953019A

公开(公告)日：1990-08-28

申请号：US440490

申请日：1989-11-22

Applicant: Akihiro Skikakura ,  Yasuyuki Tanaka ,  Makoto Shimokoriyama ,  Yoshiki Ishii ,  Tetsuya Shimizu ,  Shinichi Yamashita ,  Akio Fujii

Inventor： Akihiro Skikakura ,  Yasuyuki Tanaka ,  Makoto Shimokoriyama ,  Yoshiki Ishii ,  Tetsuya Shimizu ,  Shinichi Yamashita ,  Akio Fujii

IPC: H04N7/26 ,  H04N7/12

CPC classification number: H04N19/98

Abstract: An image signal encoding apparatus for encoding an image signal in which image of one picture plane consisting of a plurality of pixel data are divided into a plurality of blocks each consisting of a predetermined number of pixel data. For each of the blocks, a pair of reference value data regarding the maximum and minimum values of the levels of the pixel data constructing the block are formed. On the basis of the formed reference value data, encoded date is formed by encoding each of the pixel data of the block. Decoded data is formed by decoding the encoded data formed on the basis of the reference value data. By comparing each of the pixel data of the block with the decoded data, errors are detected. The reference value data are corrected in accordance with the result of the detection. Thus, the encoding errors are reduced and it is possible to perform the encoding with less deterioration in picture quality of the image signal.

Abstract translation: 一种用于编码图像信号的图像信号编码装置，其中由多个像素数据组成的一个图像的图像被划分成由预定数量的像素数据组成的多个块。 对于每个块，形成关于构成该块的像素数据的电平的最大值和最小值的一对参考值数据。 基于形成的参考值数据，通过对块的每个像素数据进行编码来形成编码日期。 通过对基于参考值数据形成的编码数据进行解码来形成解码数据。 通过将块的像素数据与解码数据进行比较，检测出错误。 参考值数据根据检测结果进行校正。 因此，编码错误减少，并且可以以较少的图像信号的图像质量劣化来执行编码。

公开(公告)号：US4951162A

公开(公告)日：1990-08-21

申请号：US116523

申请日：1987-11-03

Applicant: Katsuji Yoshimura ,  Koji Takahashi ,  Kenichi Nagasawa ,  Shinichi Yamashita ,  Motokazu Kashida ,  Mitsuhiro Otokawa

Inventor： Katsuji Yoshimura ,  Koji Takahashi ,  Kenichi Nagasawa ,  Shinichi Yamashita ,  Motokazu Kashida ,  Mitsuhiro Otokawa

IPC: G11B15/467 ,  G11B21/10

CPC classification number: G11B21/103 ,  G11B15/4678

Abstract: In an apparatus for recording an information signal on a recording medium forming many parallel tracks on the medium and for reproducing the information signal from the medium, a tracking control system is arranged to record a pilot signal of a given frequency along with the information signal in the first of the many tracks; to have the pilot signal also recorded in second and third tracks adjoining the first track on both sides thereof but at pilot signal phases shifted from the pilot signal phase of the first track to equal degrees in the directions opposite to each other at parts of the second and third tracks aligned perpendicularly to the longitudinal direction of the first track; and, in reproducing the information signal, the position of the recording medium and that of a reproducing head relative to each other are controlled on the basis of the pilot signal of the given frequency reproduced by the reproducing head from the first track along with the information signal.

Abstract translation: 在用于在介质上形成许多并行轨道的记录介质上记录信息信号并用于从介质再现信息信号的设备中，跟踪控制系统被布置成将信号信号与信息信号一起记录在一起 第一个很多轨道; 使得导频信号也记录在与其两侧相邻的第一磁道的第二和第三磁道中，但是在第二磁道的一部分处的导频信号相位从第一磁道的导频信号相位相移到相等的方向 和第三轨道，其垂直于第一轨道的纵向排列; 并且在再现信息信号时，基于由再现头从第一轨道再现的给定频率的导频信号与信息一起来控制记录介质和再现头相对于彼此的位置 信号。

公开(公告)号：US4816819A

公开(公告)日：1989-03-28

申请号：US799498

申请日：1985-11-19

Applicant: Masahiko Enari ,  Shinichi Yamashita ,  Satoshi Omata ,  Mitsutoshi Kuno ,  Hiroshi Inoue ,  Yoshiyuki Osada

Inventor： Masahiko Enari ,  Shinichi Yamashita ,  Satoshi Omata ,  Mitsutoshi Kuno ,  Hiroshi Inoue ,  Yoshiyuki Osada

IPC: G02F1/136 ,  G02F1/133 ,  G02F1/1345 ,  G02F1/1368 ,  G09G3/36

CPC classification number: G09G3/3677 ,  G09G3/3611 ,  G09G3/3666

Abstract: A display panel having N scanning lines to which scan signal are inputted and M data lines to which information signals are inputted, includes transistor groups each connecting in common plural (n) scanning lines among N scanning lines, and a selector for selecting one of N/n scanning line blocks divided by the transistor groups.

Abstract translation: 具有输入扫描信号的N条扫描线和输入信息信号的M条数据线的显示面板包括在N条扫描线中的多条（n条）扫描线共同连接的晶体管组，以及选择N / n个扫描线块由晶体管组分割。

公开(公告)号：US4714921A

公开(公告)日：1987-12-22

申请号：US823731

申请日：1986-01-29

Applicant: Hideo Kanno ,  Shinichi Yamashita ,  Masahiko Enari ,  Mitsutoshi Kuno ,  Atsushi Mizutome

Inventor： Hideo Kanno ,  Shinichi Yamashita ,  Masahiko Enari ,  Mitsutoshi Kuno ,  Atsushi Mizutome

IPC: G02F1/133 ,  G09G3/20 ,  G09G3/36 ,  G09G3/00

CPC classification number: G09G3/2011 ,  G09G3/3648 ,  G09G3/3688 ,  G09G2310/027 ,  G09G2310/0297 ,  G09G2320/0209

Abstract: A liquid crystal display panel comprising: a liquid crystal display section; an array section of switching elements connected to first information signal lines of the liquid crystal display section, respectively; a driving circuit section which divides the switching element array section into a plurality of blocks and time-sharingly drives these blocks on a block unit basis; second information signal lines of wirings as many as the number of switching elements of one block among those blocks being connected to the driving circuit section; an information signal output circuit for applying an information signal to the second information signal lines; and an arithmetic operating circuit for correcting the information signal which is applied to the second information signal line in the previous block near the next block between the previous block which is previously driven and the next block which is driven next when the panel is time-sharingly driven for every block to an information signal to eliminate a high luminance which is produced in the first information signal line connected to this second information signal line.

Abstract translation: 一种液晶显示面板，包括：液晶显示部分; 开关元件的阵列部分分别连接到液晶显示部分的第一信息信号线; 驱动电路部，其将所述开关元件阵列部分分割为多个块，并且以块为单位共享地驱动所述块; 第二信息信号线的布线数量与连接到驱动电路部分的那些块中的一个块的开关元件的数量一样多; 信息信号输出电路，用于将信息信号施加到第二信息信号线; 以及算术运算电路，用于校正在先前驱动的先前块之前的下一个块附近的先前块中的第二信息信号线的信息信号和当面板是时间共享时被下一个驱动的下一个块 驱动每个块到信息信号以消除在连接到该第二信息信号线的第一信息信号线中产生的高亮度。