Abstract:
The present invention provides a fiber Bragg Grating sequential writing method with real-time optical fiber position monitoring, characterized in that the relative phase between a fiber grating and a writing interference beam at each positioning point is determined by an interferometric side-diffraction method, and writing is sequentially performed. Accuracy in fabricating a long and complex fiber grating structure can be increased by decreasing or avoiding accumulative errors caused by long-term scan of monitoring optical fiber position, or by a means for fabricating a wanted reference fiber Bragg grating with similar settings.
Abstract:
A stator manufacturing method for a motor includes an assembling step coupling a magnetic driving assembly onto an outer circumferential wall of a shaft tube, a mold combining step disposing the shaft tube and the magnetic driving assembly in an intra-cavity of a fixture unit, a glue injecting and forming step injecting a filling glue into the intra-cavity, with the filling glue solidifying into a protective glue coating with which the shaft tube and magnetic driving assembly are coated, a mold removing step removing the fixture unit from the shaft tube, magnetic driving assembly and protective glue coating, and a shaft tube seat coupling step providing a shaft tube seat having an engaging portion and coupling the engaging portion with the shaft tube, allowing the shaft tube, the magnetic driving assembly, the protective glue coating and the shaft tube seat to be coupled together to form a stator for the motor.
Abstract:
An integrated circuit layout having a mixed track standard cell configuration that having a mixed track standard cell configuration that includes first well regions of a predetermined height and second well regions of a predetermined height, the first and second well regions are arranged within a substrate, first conductors and second conductors arranged and extending across regions of corresponding first and second well regions, and a plurality of standard cells in multiple rows. The standard cells include a first substantially equal to standard cell having a first cell height substantially equal to I(X+Y)+X or Y, wherein X is one half the predetermined height of the first well region, Y is one half the predetermined height of the second well region, and I is a positive integer.
Abstract:
An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.
Abstract:
An integrated circuit layout having a mixed track standard cell configuration that having a mixed track standard cell configuration that includes first well regions of a predetermined height and second well regions of a predetermined height, the first and second well regions are arranged within a substrate, first conductors and second conductors arranged and extending across regions of corresponding first and second well regions, and a plurality of standard cells in multiple rows. The standard cells include a first substantially equal to standard cell having a first cell height substantially equal to I(X+Y)+X or Y, wherein X is one half the predetermined height of the first well region, Y is one half the predetermined height of the second well region, and I is a positive integer.
Abstract:
The present invention relates to a display screen mask structure using a shielding frame and a manufacturing method thereof. A combination of a shielding frame body and a plurality of substrate units, or a combination of a surface-printing outer frame portion and a surface-printing separated inner frame portion of a shielding frame body to be connectively overlapped on a single or multiple layers of light-transmitting thin film substrate, is overlapped on a self-light emitting display element of a photoelectric device panel. The light, scattered from the self-light emitting display element, is filtered and reflected by and concentratedly radiated from the outer frame portion and the separated inner frame portions of the shielding frame body, so that the light radiated from the self-light emitting display element of the photoelectric device panel is more concentratedly purified and has an enhanced color contrast of the dark tone.
Abstract:
A method for making a water-proof laminate from wood, includes a lower mold. A lower cover is provided in the lower mold. A wood plate is provided on the lower cover in the lower mold. An upper cover is provided on the wood plate. An upper mold is provided for pressing the lower cover, the wood plate and lower cover against the lower mold. A coating is injected into the upper and lower molds to cover at least the edges of the upper mold, wood plate and lower mold so that a water-proof laminate is finished after the curing of the coating. The upper mold is moved from the lower mold, and the water-proof laminate is moved from the lower mold.
Abstract:
A multi-layer chopping board includes a main body having a plurality of regular planks and a reinforced plank stacked upon another, and a cover layer sheathed on a peripheral side of the main body to couple the planks. The reinforced plank is made of a material more inflexible than that of each regular plank. The cover layer is made of a material different from that of any of the planks.