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    SCR/MOS CLAMP FOR ESD PROTECTION OF INTEGRATED CIRCUITS
    11.
    发明申请
    SCR/MOS CLAMP FOR ESD PROTECTION OF INTEGRATED CIRCUITS 失效
    用于ESD保护集成电路的SCR / MOS钳位

    公开(公告)号：US20120305984A1

    公开(公告)日：2012-12-06

    申请号：US13149174

    申请日：2011-05-31

    申请人： John B. Campi, JR. ,  Shunhua T. Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Junjun Li ,  Rahul Mishra ,  Mujahid Muhammad

    发明人： John B. Campi, JR. ,  Shunhua T. Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Junjun Li ,  Rahul Mishra ,  Mujahid Muhammad

    IPC分类号： H01L29/747 ,  G06F17/50 ,  H01L21/332

    CPC分类号： H01L29/742 ,  H01L27/0262

    摘要： An electrostatic discharge (ESD) protection circuit, methods of fabricating an ESD protection circuit, methods of providing ESD protection, and design structures for an ESD protection circuit. An NFET may be formed in a p-well and a PFET may be formed in an n-well. A butted p-n junction formed between the p-well and n-well results in an NPNP structure that forms an SCR integrated with the NFET and PFET. The NFET, PFET and SCR are configured to collectively protect a pad, such as a power pad, from ESD events. During normal operation, the NFET, PFET, and SCR are biased by an RC-trigger circuit so that the ESD protection circuit is in a high impedance state. During an ESD event while the chip is unpowered, the RC-trigger circuit outputs trigger signals that cause the SCR, NFET, and PFET to enter into conductive states and cooperatively to shunt ESD currents away from the protected pad.

    摘要翻译： 静电放电（ESD）保护电路，制造ESD保护电路的方法，提供ESD保护的方法以及ESD保护电路的设计结构。 可以在p阱中形成NFET，并且可以在n阱中形成PFET。 在p阱和n阱之间形成的对接p-n结导致形成与NFET和PFET集成的SCR的NPNP结构。 NFET，PFET和SCR被配置为共同保护诸如电源板的焊盘免受ESD事件的影响。 在正常工作期间，NFET，PFET和SCR被RC触发电路偏置，使得ESD保护电路处于高阻抗状态。 在芯片无电源时的ESD事件期间，RC触发电路输出触发信号，使SCR，NFET和PFET进入导通状态，并协同地将ESD电流从受保护的焊盘分流。

    Low leakage, low capacitance electrostatic discharge (ESD) silicon controlled recitifer (SCR), methods of manufacture and design structure
    14.
    发明授权
    Low leakage, low capacitance electrostatic discharge (ESD) silicon controlled recitifer (SCR), methods of manufacture and design structure 有权
    低泄漏，低电容静电放电（ESD）硅控制背光（SCR），制造方法和设计结构

    公开(公告)号：US08796731B2

    公开(公告)日：2014-08-05

    申请号：US12859801

    申请日：2010-08-20

    申请人： Michel J. Abou-Khalil ,  Shunhua T. Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Junjun Li ,  Mujahid Muhammad

    发明人： Michel J. Abou-Khalil ,  Shunhua T. Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Junjun Li ,  Mujahid Muhammad

    IPC分类号： H01L29/861

    CPC分类号： H01L29/7412 ,  H01L27/0262

    摘要： A low leakage, low capacitance diode based triggered electrostatic discharge (ESD) silicon controlled rectifiers (SCR), methods of manufacture and design structure are provided. The method includes providing a silicon film on an insulator layer. The method further includes forming isolation regions which extend from an upper side of the silicon layer to the insulator layer. The method further includes forming one or more diodes in the silicon layer, including a p+ region and an n+ region formed in a well bordered by the isolation regions. The isolation regions isolate the one or more diodes in a vertical direction and the insulator layer isolates the one or more diodes from an underlying P or N type substrate, in a horizontal direction.

    摘要翻译： 提供了低泄漏，低电容二极管的触发静电放电（ESD）硅控整流器（SCR），制造方法和设计结构。 该方法包括在绝缘体层上提供硅膜。 该方法还包括形成从硅层的上侧延伸到绝缘体层的隔离区域。 该方法还包括在硅层中形成一个或多个二极管，包括形成在由隔离区界定的阱中的p +区和n +区。 隔离区域沿垂直方向隔离一个或多个二极管，并且绝缘体层在水平方向上将一个或多个二极管与下面的P或N型衬底隔离。

    Low trigger voltage electrostatic discharge NFET in triple well CMOS technology
    17.
    发明授权
    Low trigger voltage electrostatic discharge NFET in triple well CMOS technology 有权
    低触发电压静电放电NFET三阱CMOS技术

    公开(公告)号：US08350329B2

    公开(公告)日：2013-01-08

    申请号：US12907105

    申请日：2010-10-19

    申请人： John B. Campi, Jr. ,  Shunhua T. Chang ,  Kiran V. Chatty ,  Robert J Gauthier, Jr. ,  Junjun Li ,  Rahul Mishra ,  Mujahid Muhammad

    发明人： John B. Campi, Jr. ,  Shunhua T. Chang ,  Kiran V. Chatty ,  Robert J Gauthier, Jr. ,  Junjun Li ,  Rahul Mishra ,  Mujahid Muhammad

    IPC分类号： H01L23/60 ,  H01L21/8238

    CPC分类号： H01L27/0274

    摘要： An electrostatic discharge (ESD) protection device for an integrated circuit includes a buried layer of a first polarity type formed in a substrate of a second polarity type. A well region of the second polarity type is formed above the buried layer. An FET of the first polarity type is formed within the well region. An inner pair of shallow wells of the first polarity type is disposed adjacent to source and drain diffusion regions of the FET, the inner pair of shallow wells having a depth such that a bottom of the inner pair of shallow wells is above a top of the buried layer. An outer pair of deep wells of the first polarity type extends down to the top of the buried layer such that the outer pair of deep wells and the buried layer define a perimeter of the well region of the second polarity type.

    摘要翻译： 用于集成电路的静电放电（ESD）保护装置包括形成在第二极性类型的衬底中的第一极性类型的掩埋层。 第二极性类型的阱区形成在掩埋层的上方。 在阱区内形成第一极性类型的FET。 第一极性类型的内部一对浅阱设置在FET的源极和漏极扩散区附近，内部一对浅阱具有使得内部一对浅井的底部高于 埋层 第一极性类型的一对深阱对向下延伸到掩埋层的顶部，使得外部一对深阱和掩埋层限定第二极性类型的阱区的周边。

    Low trigger voltage electrostatic discharge NFET in triple well CMOS technology
    18.
    发明申请
    Low trigger voltage electrostatic discharge NFET in triple well CMOS technology 有权
    低触发电压静电放电NFET三阱CMOS技术

    公开(公告)号：US20120091530A1

    公开(公告)日：2012-04-19

    申请号：US12907105

    申请日：2010-10-19

    申请人： John B. Campi, JR. ,  Shunhua T. Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Junjun Li ,  Rahul Mishra ,  Mujahid Muhammad

    发明人： John B. Campi, JR. ,  Shunhua T. Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Junjun Li ,  Rahul Mishra ,  Mujahid Muhammad

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L27/0274

    摘要： An electrostatic discharge (ESD) protection device for an integrated circuit includes a buried layer of a first polarity type formed in a substrate of a second polarity type. A well region of the second polarity type is formed above the buried layer. An FET of the first polarity type is formed within the well region. An inner pair of shallow wells of the first polarity type is disposed adjacent to source and drain diffusion regions of the FET, the inner pair of shallow wells having a depth such that a bottom of the inner pair of shallow wells is above a top of the buried layer. An outer pair of deep wells of the first polarity type extends down to the top of the buried layer such that the outer pair of deep wells and the buried layer define a perimeter of the well region of the second polarity type.

    摘要翻译： 用于集成电路的静电放电（ESD）保护装置包括形成在第二极性类型的衬底中的第一极性类型的掩埋层。 第二极性类型的阱区形成在掩埋层的上方。 在阱区内形成第一极性类型的FET。 第一极性类型的内部一对浅阱设置在FET的源极和漏极扩散区附近，内部一对浅阱具有使得内部一对浅井的底部高于 埋层 第一极性类型的一对深阱对向下延伸到掩埋层的顶部，使得外部一对深阱和掩埋层限定第二极性类型的阱区的周边。

    Electrical Overstress Protection Circuit
    19.
    发明申请
    Electrical Overstress Protection Circuit 有权
    电气过载保护电路

    公开(公告)号：US20100246076A1

    公开(公告)日：2010-09-30

    申请号：US12632015

    申请日：2009-12-07

    申请人： John B. Campi, JR. ,  Shunhua T. Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Junjun Li ,  Mujahid Muhammad

    发明人： John B. Campi, JR. ,  Shunhua T. Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Junjun Li ,  Mujahid Muhammad

    IPC分类号： H02H9/00 ,  G06F17/50

    CPC分类号： H01L27/0251 ,  G06F17/5045

    摘要： A semiconductor circuit for electric overstress (EOS) protection is provided. The semiconductor circuit employs an electrostatic discharge (ESD) protection circuit, which has a resistor-capacitor (RC) time-delay network connected to a discharge capacitor. An electronic component that has voltage snapback property or a diodic behavior is connected to alter the logic state of the gate of the discharge transistor under an EOS event. Particularly, the electronic component is configured to turn on the gate of the discharge capacitor throughout the duration of an electrical overstress (EOS) condition as well as throughout the duration of an ESD event. A design structure may be employed to design or manufacture a semiconductor circuit that provides protection against an EOS condition without time limitation, i.e., without being limited by the time constant of the RC time delay network for EOS events that last longer than 1 microsecond.

    摘要翻译： 提供了一种用于电力过应力（EOS）保护的半导体电路。 半导体电路采用静电放电（ESD）保护电路，其具有连接到放电电容器的电阻 - 电容（RC）延时网络。 连接具有电压骤回特性或二极管行为的电子部件，以改变在EOS事件下放电晶体管的栅极的逻辑状态。 特别地，电子部件被配置成在电应力（EOS）条件以及ESD事件的整个持续时间期间打开放电电容器的栅极。 可以采用设计结构来设计或制造半导体电路，该半导体电路在没有时间限制的情况下提供针对EOS状态的保护，即不受时间长度超过1微秒的EOS事件的RC时间延迟网络的时间常数的限制。

    Active ESD Protection
    20.
    发明申请
    Active ESD Protection 审中-公开
    主动ESD保护

    公开(公告)号：US20070297105A1

    公开(公告)日：2007-12-27

    申请号：US11426021

    申请日：2006-06-23

    申请人： Ciaran J. Brennan ,  Shunhua T. Chang

    发明人： Ciaran J. Brennan ,  Shunhua T. Chang

    IPC分类号： H02H9/00

    CPC分类号： H01L27/0251

    摘要： A system and method of electrostatic discharge (ESD) protection in a logic circuit using either state manipulation or current injection. A first system is disclosed that includes an ESD detection circuit for detecting an ESD event; and an ESD control circuit that can change a state of the logic circuit from a normal mode to an ESD mode in response to a signal received from the ESD detection circuit. A second system is disclosed that includes an attenuator circuit coupled to a chip pad; and a switch for diverting current from the attenuator circuit to an internal node of the logic circuit during an ESD event to reduce a voltage at the chip pad.

    摘要翻译： 使用状态操作或电流注入的逻辑电路中的静电放电（ESD）保护的系统和方法。 公开了一种包括用于检测ESD事件的ESD检测电路的第一系统; 以及ESD控制电路，其可以响应于从ESD检测电路接收的信号，将逻辑电路的状态从正常模式改变为ESD模式。 公开了一种第二系统，其包括耦合到芯片焊盘的衰减器电路; 以及用于在ESD事件期间将电流从衰减器电路转移到逻辑电路的内部节点的开关，以减小芯片焊盘处的电压。