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公开(公告)号：US12225126B2
公开(公告)日：2025-02-11
申请号：US18076615
申请日：2022-12-07
Applicant: Silicon Motion, Inc.
Inventor： Wun-Jhe Wu , Po-Hung Chen , Chiao-Wen Cheng , Jiun-Hung Yu , Chih-Wei Liu
Abstract: The invention introduces an apparatus for detecting errors during data encryption. The apparatus includes a key generation circuitry and a key-error detection circuitry. The key generation circuitry is arranged operably to realize a key expansion operation for generating multiple round keys based on a root key in an encryption algorithm, where the encryption algorithm encodes plaintext or an intermediate encryption result with one round key in a corresponding round. The error detection circuitry is arranged operably to: calculate redundant data corresponding to each round key; and output an error signal to a processing unit when finding that any round key does not match corresponding redundant data at a check point during the key expansion operation.
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公开(公告)号：US12204763B2
公开(公告)日：2025-01-21
申请号：US18080852
申请日：2022-12-14
Applicant: Silicon Motion, Inc.
Inventor： Chun-Yi Chen , Hsiao-Te Chang
Abstract: The invention relates to a method, a non-transitory computer-readable storage medium and an apparatus for dynamically updating an optimization read voltage (RV) table. The method includes: obtaining a data-read transaction and replying with the data-read transaction to a host side after listening to a first request for read-performance data, which is issued by the host side, thereby enabling the data-performance transaction to be used in an update of the optimization RV table for a designated memory-cell type; and programming multiple records of an updated optimization RV table for the designated memory-cell type into a designated location of the NAND-flash module after listening to a second request for updating the optimization RV table for the designated memory-cell type, which is issued by the host side. The data-read transaction includes a current environmental parameter of a NAND-flash module, the designated memory-cell type and a bit error rate (BER). Each record includes one set of RV parameters and an environmental parameter associated with the set of RV parameters.
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13.发明授权公开(公告)号：US12189991B2
公开(公告)日：2025-01-07
申请号：US17958430
申请日：2022-10-02
Applicant: Silicon Motion, Inc.
Inventor： Li-Chi Chen , Yen-Yu Jou
IPC: G06F3/06
Abstract: A method of a storage device controller includes: using an interface circuit for receiving and storing different write address information of different write command signals sent from a host device, the different write address information being out of sequence; and, using multiple processor cores to rearrange the different write address information in sequence and then write data into at least one storage zone according to the different write address information rearranged in sequence.
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公开(公告)号：US20250006252A1
公开(公告)日：2025-01-02
申请号：US18621085
申请日：2024-03-28
Applicant: Silicon Motion, Inc.
Inventor： Tsung-Chieh Yang
IPC: G11C11/4096 , G11C11/4093 , G11C29/52
Abstract: A data programming method for a flash memory includes: writing a write data to a page buffer of the flash memory; encoding the write data to generate first parity data corresponding to the write data, and writing the first parity data to the page buffer; while generating the first parity data, performing an error detection based on the write data and the first parity data to produce an error detection result; and when the error detection result indicates that there is no error in the first parity data, issuing a program command to the flash memory to program the write data and the first parity data in the page buffer into a flash memory element of the flash memory.
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公开(公告)号：US20240428867A1
公开(公告)日：2024-12-26
申请号：US18746496
申请日：2024-06-18
Applicant: Silicon Motion, Inc.
Inventor： Wen-Chun CHANG
Abstract: A data storage device is adaptively adjusted according to the sensed temperature. The data storage device has a first clock generator and a second clock generator, respectively generating a first clock and a second clock, which are selected by a controller to operate a nonvolatile memory. In response to the sensed temperature not exceeding a first threshold temperature, the controller selects the first clock to operate the non-volatile memory. In response to the sensed temperature exceeding the first threshold temperature, the controller alternately selects the first clock and the second clock to operate the non-volatile memory.
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Patent Agency Ranking
公开(公告)号：US12164805B2
公开(公告)日：2024-12-10
申请号：US17679116
申请日：2022-02-24
Applicant: Silicon Motion, Inc.
Inventor： Tsu-Han Lu , Hsiao-Chang Yen
Abstract: A flash memory scheme simplifies the command sequences transmitted between a flash memory device and a flash memory controller into a simplified command sequence so as to reduce the waiting time period of the command transmission and improve the performance of flash memory.
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公开(公告)号：US20240402910A1
公开(公告)日：2024-12-05
申请号：US18203075
申请日：2023-05-30
Applicant: Silicon Motion, Inc.
Inventor： Tsu-Han Lu , Hsiao-Chang Yen
IPC: G06F3/06
Abstract: A flash memory controller is used in a storage device and coupled to a flash memory device of the storage device through a specific communication interface and includes an input/output (I/O) circuit and a processor. The I/O circuit is used for sending commands and data between the flash memory device and the processor. The processor is used for controlling the I/O circuit sending a specific boundary check command signal or a specific boundary check set-feature signal via the specific communication interface to the flash memory device, to make the flash memory device read out more page data of multiple page units from a specific block in the memory cell array based on a smaller search range and to make the flash memory device determine whether the multiple page units are empty pages; the search range can be defined by a start page address stored in the flash memory device.
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公开(公告)号：US20240394155A1
公开(公告)日：2024-11-28
申请号：US18202297
申请日：2023-05-26
Applicant: Silicon Motion, Inc.
Inventor： Jie-Hao Lee , Chun-Ju Chen , Po-Ting Chen
Abstract: A method for performing data access management of a memory device in predetermined communications architecture to enhance sudden power off recovery (SPOR) of page-group-based redundant array of independent disks (RAID) protection with aid of suspendible serial number and associated apparatus are provided. The method may include: utilizing the memory controller to write preceding data and metadata thereof into at least one set of preceding pages in a first active block to make the metadata carry at least one preceding serial number; writing dummy data and other metadata into at least one set of dummy pages in the first active block to make the other metadata carry at least one suspended serial number which is equal to a last serial number among the at least one preceding serial number; and utilizing the memory controller to write subsequent data and metadata thereof to make it carry at least one subsequent serial number.
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19.发明授权公开(公告)号：US12153820B2
公开(公告)日：2024-11-26
申请号：US17206147
申请日：2021-03-19
Applicant: Silicon Motion, Inc.
Inventor： Tzu-Yi Yang
Abstract: A method of performing a wear-leveling operation in a flash memory includes: determining a block age for each of a plurality of blocks in the flash memory according to a number of erase operations that have been performed on the flash memory after the block is erased; selecting one or more candidate source blocks from the plurality of blocks by comparing block ages of the plurality of blocks with an age limit; determining a source block from the one or more candidate source blocks according to erase counts or block ages of the one or more candidate source blocks; and performing the wear-leveling operation on the source block.
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公开(公告)号：US20240386970A1
公开(公告)日：2024-11-21
申请号：US18784972
申请日：2024-07-26
Applicant: Silicon Motion, Inc.
Inventor： Tsung-Chieh Yang
Abstract: A method for reading data stored in a flash memory includes at least the following steps: controlling the flash memory to perform a plurality of read operations upon a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from the memory cells by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences.
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