Abstract:
A plasma display panel (PDP) having high efficiency includes a front substrate and a rear substrate facing each other; element portions interposed between the front and rear substrates, and including a first element and a second element disposed in both sides of a main discharge space and a third and a fourth element respectively having a narrow width and protruding on the first element and the second element, wherein the first and second elements, and the third and fourth elements partition stepped spaces along a stepped surface in the main discharge space; sustain electrode pairs alternately disposed on the front substrate, extending along a first direction and causing mutual discharge; dielectric layers which are formed on the front substrate to cover the sustain electrode pairs and in which grooves are formed along a direction that is substantially perpendicular to the first direction; and address electrodes formed on the rear substrate and extending in a second direction that crosses the first direction.
Abstract:
A plasma display panel (PDP) is disclosed. In one embodiment, the PDP includes: i) first and second substrates facing each other, ii) a plurality of first barrier ribs formed between the first and second substrates and configured to define a plurality of discharge cells and iii) a plurality of second barrier ribs dividing each of the discharge cells into a first sub-discharge cell and a second sub-discharge cell, wherein a phosphor layer is formed in the first sub-discharge cells and is not formed in the second sub-discharge cells. According to one embodiment, the PDP has high driving efficiency obtained by improving an address voltage margin, and high image quality obtained by removing noise brightness caused by discharge light resulting from an address discharge, and is suitable for an image display with high efficiency and high resolution.
Abstract:
A plasma display panel comprises: first and second substrates facing each other; a plurality of barrier ribs partitioning a discharge space between the first and second substrates so as to define a plurality of discharge cells; address electrodes extending in parallel with each other and in a predetermined direction; first and second electrodes disposed on the second substrate in a direction intersecting the direction of the address electrodes, the first and second electrodes being separated from the address electrodes, the first and second electrodes being provided in correspondence with each of the discharge cells; and phosphor layers coated on the discharge cells. The first and second electrodes protrude in a direction from the second substrate to the first substrate, and face each other so as to provide a space therebetween.
Abstract:
An organic electroluminescence device is described and includes a transparent substrate with a first electrode formed on the top surface of the transparent substrate in a predetermined pattern. The first electrode is transparent. An organic layer includes a hole injecting layer, a hole transporting layer, an emitting layer, and an electron transporting layer. They are sequentially stacked on the top surface of the first electrode. A second electrode is formed on the top surface of the organic layer in a predetermined pattern. The distance from the top surface of the hole transporting layer to the bottom surface of the second electrode ranges from about 350 Å to about 450 Å such that the color purity and brightness of blue light is optimized. Accordingly, the organic electroluminescence device increases the color purity and brightness of blue light, thereby providing an image having excellent picture quality.
Abstract:
Provided is a heat-strengthened vacuum glass, comprising: a plurality of sheet glasses spaced apart by a predetermined interval; a plurality of spacers interposed between the sheet glasses to maintain the intervals between the sheet glasses; and a sealing material arranged along edges of the sheet glasses to seal and bond the sheet glasses. The heat-strengthened vacuum glass of the present invention has a surface compressive stress of 20 Mpa to 55 Mpa after the seal bonding of the sheet glasses, thus ensuring high thermal resistance, high strength, and, when damaged, high stability.
Abstract:
A Plasma Display Panel (PDP) has a high aperture ratio of a discharge cell, a high light transmittance, and a high luminous efficiency and a stable and efficient discharge occurs uniformly at a low driving voltage on inner sidewalls of the discharge cell and concentrates in the center of the discharge cell. The PDP includes: a front substrate and a rear substrate facing each other and separated from each other; barrier ribs of a dielectric material arranged between the front substrate and the rear substrate to define discharge cells together with the front substrate and the rear substrate; discharge electrodes arranged within the barrier ribs, the discharge electrodes being separated from each other and surrounding the discharge cells and having at least one corner portion for surrounding the discharge cells; fluorescent layers arranged in the discharge cells; a discharge gas contained within the discharge cells; and an attenuator adapted to reduce a strength of an electric field generated between at least one pair of corner portions of the discharge electrodes, the corner portions facing each other, to be less than a strength of an electric field generated between portions of the discharge electrodes facing each other, other than the corner portions, in the discharge cells.
Abstract:
Provided in the present invention is a vacuum glass, comprising: a plurality of plate glasses arranged to be spaced apart at fixed distances; a sealing material provided along edges of the plate glasses to seal and adhere to the plate glasses; and a plurality of pillars arranged between the plate glasses to maintain the distances between the plate glasses. The plurality of pillars are arranged at different arrangement distances in vertical and horizontal directions. Thus, the thermal insulation performance of the vacuum glass may be improved, and stress applied to the vacuum glass may be reduced by the pillars to secure the safety of a product.
Abstract:
A photoelectric conversion device designed according to a ratio of a line width to a pitch of a grid collector electrode is provided. The photoelectric conversion device includes a first substrate, a second substrate facing the first substrate, and a first electrode between the first substrate and the second substrate, the first electrode including a first grid electrode. A first ratio (W/P) of a line width of the first grid electrode to a pitch of the first grid electrode is configured in accordance with a photoelectric conversion efficiency of the photoelectric conversion device, thereby the photoelectric conversion device may have improved photoelectric conversion efficiency.
Abstract:
A plasma display panel (PDP) includes a front substrate and a rear substrate that face each other; a pair of base portions disposed between the front substrate and the rear substrate and are concavely indented in directions away from each other; a pair of barrier walls disposed on the pair of base portions to define a discharge cell; a scan electrode and a sustain electrode that generate a mutual discharge in the discharge cell; an address electrode to cross the scan electrode and that generates an address discharge together with the scan electrode; a phosphor layer disposed in the discharge cell; and a discharge gas injected into the discharge cell.
Abstract:
A thin film transistor (TFT), a method of fabricating the same, and an organic light emitting diode (OLED) display device including the TFT. The TFT includes a substrate having a pixel region and a non-pixel region, a semiconductor layer, a gate insulating layer, a gate electrode, and source and drain electrodes disposed on the pixel region, at least one gettering site disposed on the non-pixel region, and at least one connection portion to connect the at least one gettering site and the semiconductor layer The method of fabricating the TFT includes patterning a polycrystalline silicon (poly-Si) layer to form a plurality of semiconductor layers, connection portions, and at least one gettering site, the semiconductor layers being connected to the at least one gettering site via the connection portions, and annealing the substrate to getter the plurality of semiconductor layers.