公开(公告)号：US06472286B1

公开(公告)日：2002-10-29

申请号：US09635583

申请日：2000-08-09

申请人： Ta-Lee Yu

发明人： Ta-Lee Yu

IPC分类号： H01L21331

CPC分类号： H01L29/7322 ,  H01L27/0259

摘要： The invention describes the fabrication and structure of an ESD protection device for integrated circuit semiconductor devices with improved ESD protection and resiliency. A vertical bipolar npn transistor forms the basis of the protection device. To handle the large current requirements of an ESD incident, the bipolar transistor has multiple base and emitter elements formed in an npn bipolar array. To assure turn-on of the multiple elements of the array the emitter fingers are continuously or contiguously connected with an unique emitter design layout. The contiguous emitter design provides an improved electrical emitter connection for the device, minimizing any unbalance that can potentially occur when using separate emitter fingers and improving the ability for the simultaneous turn on of the multiple emitter-base elements. The emitter is contained within the footprint of the collector elements, and enables containment of device size, therefore minimizing device capacitance characteristics important in high speed circuit design. Other embodiments of the invention use variations in the structure of the common contiguous emitter conductor as well as different base conductor structure layouts.

摘要翻译： 本发明描述了具有改进的ESD保护和弹性的集成电路半导体器件的ESD保护器件的制造和结构。 垂直双极性npn晶体管构成保护器件的基础。 为了处理ESD事件的大电流要求，双极晶体管具有以npn双极阵列形成的多个基极和发射极元件。 为了确保阵列的多个元件的导通，发射器指状物连续地或连续地连接着独特的发射器设计布局。 连续的发射器设计为器件提供了改进的发射极连接，使使用分离的发射极手指时可能发生的任何不平衡最小化，并提高了多个发射极 - 基极元件同时导通的能力。 发射极包含在集电极元件的占地面积内，并且能够容纳器件尺寸，从而最大程度地降低了高速电路设计中重要的器件电容特性。 本发明的其它实施例使用公共连续发射极导体的结构的变化以及不同的基底导体结构布局。

公开(公告)号：US5986307A

公开(公告)日：1999-11-16

申请号：US93426

申请日：1998-06-08

申请人： Ta-Lee Yu

发明人： Ta-Lee Yu

IPC分类号： H01L27/02 ,  H01L23/62

CPC分类号： H01L27/0262 ,  H01L27/0259 ,  H01L27/0266

摘要： A silicon-rectifier integral with either an NMOS transistor or a PMOS transistor (together which constitute an output buffer) is disclosed. If integral with the NMOS transistor, the silicon-controlled rectifier is provided with the emitter and base of the NPN bipolar junction transistor acting as the source and bulk of the NMOS transistor. On the other hand, if integral with the PMOS transistor, the silicon-controlled rectifier is provided with the emitter and base of the PNP bipolar junction transistor acting as the source and bulk of the PMOS transistor.

摘要翻译： 公开了与NMOS晶体管或PMOS晶体管（一起构成输出缓冲器）集成的硅整流器。 如果与NMOS晶体管集成，则可控硅整流器具有作为NMOS晶体管的源极和体的NPN双极结晶体管的发射极和基极。 另一方面，如果与PMOS晶体管集成，则可控硅整流器具有用作PMOS晶体管的源极和体的PNP双极结晶体管的发射极和基极。

公开(公告)号：US5962876A

公开(公告)日：1999-10-05

申请号：US055619

申请日：1998-04-06

申请人： Ta-Lee Yu

发明人： Ta-Lee Yu

IPC分类号： H01L27/02 ,  H01L29/74 ,  H01L31/111

CPC分类号： H01L27/0248

摘要： An electrostatic discharge protection circuit comprises a semiconductor layer of a first conductivity type, a floating semiconductor layer of a second conductivity type, a first doped region of the first conductivity type, a first doped region of the second conductivity type, a second doped region of the second conductivity type, a gate structure, and a second doped region of the first conductivity type. The floating semiconductor layer of a second conductivity type is in contact with the semiconductor layer of a first conductivity type to establish a junction therebetween. The first doped region of the first conductivity type is formed in the semiconductor layer of a second conductivity type and connected to a first node. The first doped region of the second conductivity type is formed in the semiconductor layer of a first conductivity type and connected to a second node. The second doped region of the second conductivity type spans the junction. The gate structure overlies a portion of the semiconductor layer of a first conductivity type between those doped regions of the second conductivity type. The second doped region of the first conductivity type is formed in the semiconductor layer of a first conductivity type and connected to the second node. The second doped region of the second conductivity type will break down to trigger the conduction of a discharge current flowing through the junction when electrostatic discharge stress occurs between the first node and the second node.

摘要翻译： 静电放电保护电路包括第一导电类型的半导体层，第二导电类型的浮置半导体层，第一导电类型的第一掺杂区，第二导电类型的第一掺杂区，第二导电类型的第一掺杂区， 第二导电类型，栅极结构和第一导电类型的第二掺杂区域。 第二导电类型的浮置半导体层与第一导电类型的半导体层接触以在它们之间建立连接。 第一导电类型的第一掺杂区域形成在第二导电类型的半导体层中，并连接到第一节点。 第二导电类型的第一掺杂区形成在第一导电类型的半导体层中，并连接到第二节点。 第二导电类型的第二掺杂区跨越结。 栅极结构覆盖第二导电类型的那些掺杂区域之间的第一导电类型的半导体层的一部分。 第一导电类型的第二掺杂区域形成在第一导电类型的半导体层中，并连接到第二节点。 当在第一节点和第二节点之间产生静电放电应力时，第二导电类型的第二掺杂区域将分解以触发流过该结的放电电流的导通。

公开(公告)号：US5949634A

公开(公告)日：1999-09-07

申请号：US55618

申请日：1998-04-06

申请人： Ta-Lee Yu

发明人： Ta-Lee Yu

IPC分类号： H01L27/02 ,  H02H3/00

CPC分类号： H01L27/0262 ,  H01L27/0266 ,  H01L2924/0002

摘要： An electrostatic discharge protection circuit comprises an NMOS transistor and a silicon-controlled rectifier. The NMOS transistor is configured with one source/drain region connected to a first node, and its gate as well as another source/drain region connected to a second node. The silicon-controlled rectifier comprises a PNP transistor, an NPN transistor, and a resistor. The PNP transistor is provided with a first emitter connected to the first node, a first base disconnected from the first node, and a first collector. The NPN transistor is provided with a second emitter connected to the second node, a second base connected to the first collector and a second collector connected to the first base. However, the resistor is connected between the second base and the second node. The NMOS transistor enters breakdown to trigger the silicon-controlled rectifier to conduct a discharge current when electrostatic discharge stress occurs between the first node and the second node.

摘要翻译： 静电放电保护电路包括NMOS晶体管和可控硅整流器。 NMOS晶体管配置有连接到第一节点的一个源极/漏极区域，以及其栅极以及连接到第二节点的另一个源极/漏极区域。 硅控整流器包括PNP晶体管，NPN晶体管和电阻器。 PNP晶体管设置有连接到第一节点的第一发射器，与第一节点断开的第一基座和第一收集器。 NPN晶体管设置有连接到第二节点的第二发射极，连接到第一集电极的第二基极和连接到第一基极的第二集电极。 然而，电阻器连接在第二基座和第二节点之间。 当在第一节点和第二节点之间发生静电放电应力时，NMOS晶体管进入击穿以触发可控硅整流器以导通放电电流。

公开(公告)号：US5909347A

公开(公告)日：1999-06-01

申请号：US73163

申请日：1998-05-05

申请人： Ta-Lee Yu

发明人： Ta-Lee Yu

IPC分类号： H01L27/02 ,  H02H9/00

CPC分类号： H01L27/0262 ,  H01L27/0251

摘要： An electrostatic discharge protection circuit protects an internal circuit that is coupled to a pad from electrostatic discharge damage. The electrostatic discharge protection circuit comprises a PNP transistor, a NPN transistor, and a P-type flash memory cell. The PNP and NPN transistors have an emitter, a base, and a collector, respectively. The PNP transistor is configured with its emitter connected to a power node, its base connected to the collector of the NPN transistor, its collector connected to the base of the NPN transistor. The emitter of the NPN transistor is connected to a circuit node. The flash memory cell is configured with a drain connected to the base of the NPN transistor, a source connected to the power node, and a control gate coupled to the power node. When electrostatic discharge stress occurs at the pad, the P-type flash memory cell enters breakdown to be programmed and triggers the conduction of the transistors.

摘要翻译： 静电放电保护电路保护耦合到焊盘的内部电路免受静电放电损坏。 静电放电保护电路包括PNP晶体管，NPN晶体管和P型闪存单元。 PNP和NPN晶体管分别具有发射极，基极和集电极。 PNP晶体管配置有其发射极连接到功率节点，其基极连接到NPN晶体管的集电极，其集电极连接到NPN晶体管的基极。 NPN晶体管的发射极连接到电路节点。 闪存单元配置有连接到NPN晶体管的基极的漏极，连接到功率节点的源极和耦合到功率节点的控制栅极。 当在焊盘处发生静电放电应力时，P型闪存单元进入击穿以进行编程，并触发晶体管的导通。

公开(公告)号：US5831316A

公开(公告)日：1998-11-03

申请号：US778081

申请日：1997-01-02

申请人： Ta-Lee Yu ,  Konrad Young

发明人： Ta-Lee Yu ,  Konrad Young

IPC分类号： H01L27/02 ,  H01L27/088 ,  H01L29/78 ,  H01L29/00

CPC分类号： H01L27/0277 ,  H01L27/088 ,  H01L29/7831 ,  H01L2924/0002

摘要： A multi-finger MOS transistor element is provided in which all of the base resistance values of parasitic bipolar transistors (NPN, if an NMOS, or PNP, if a PMOS transistor) in each finger MOS are equal to each other. Thus, each finger MOS transistor element in the multi-finger MOS transistor is turned on simultaneously to enhance ESD protection performance. In the multi-finger MOS transistor, the diffusion region for providing the well/substrate contact is distributed in the source region to make the base resistance value of the parasitic NPN (or PNP) transistor in each finger MOS equal to each other. The multi-finger MOS of the invention includes a plurality of drain regions, each having drain contacts, a plurality of source regions, each having source contacts, and a plurality of gate regions, wherein each gate region is between each drain region and the source region; a bias diffusion region formed in the source region along a middle line which is equally spaced between the pair of gate regions.

摘要翻译： 提供了多指MOS晶体管元件，其中每个指状MOS中的寄生双极晶体管（NPN，如果NMOS或PNP，如果PMOS晶体管）的所有基极电阻值彼此相等。 因此，多指MOS晶体管中的每个指状MOS晶体管元件同时导通，以增强ESD保护性能。 在多指MOS晶体管中，用于提供阱/衬底接触的扩散区域分布在源极区域中，以使每个手指MOS中的寄生NPN（或PNP）晶体管的基极电阻值彼此相等。 本发明的多指状MOS包括多个漏极区，每个具有漏极接触，多个源极区，每个具有源极接触，以及多个栅极区，其中每个栅极区在每个漏极区和源极之间 地区; 偏置扩散区，形成在沿着中间线的源极区中，所述中间线在所述一对栅极区之间间隔开。

公开(公告)号：US5777368A

公开(公告)日：1998-07-07

申请号：US648225

申请日：1996-05-13

申请人： Chau-Neng Wu ,  Ta-Lee Yu ,  Alex Wang

发明人： Chau-Neng Wu ,  Ta-Lee Yu ,  Alex Wang

IPC分类号： H01L27/02 ,  H01L27/092 ,  H01L23/62 ,  H01L29/41

CPC分类号： H01L27/0928 ,  H01L27/0248 ,  H01L27/0266

摘要： An electrostatic discharge (ESD) protection device includes a drain region and a source region, each having a heavily-doped region and a lightly-doped region, wherein the junction depth of the lightly-doped region is deeper than that of the heavily doped region. Accordingly, the ESD current density will be decreased owing to the enlarged junction area during the ESD event. In addition, the heat dissipation can be spread over the enlarged junction area instead of being focused on the drain cylindrical edge. Moreover, low parasitic capacitance in the bond pad is achieved because the junction capacitance of the lightly-doped region is smaller than that of the heavily-doped region. Furthermore, conducting blocks are arranged between the lightly-doped regions and the source/drain electrodes, respectively, to prevent the metal melt filament from spiking the junction.

摘要翻译： 静电放电（ESD）保护器件包括漏极区域和源极区域，每个区域具有重掺杂区域和轻掺杂区域，其中轻掺杂区域的结深度比重掺杂区域的深度深 。 因此，由于ESD事件期间扩大的接合面积，ESD电流密度将降低。 此外，散热可以扩展在扩大的接合面积上，而不是聚焦在排水圆柱形边缘上。 此外，由于轻掺杂区域的结电容小于重掺杂区域的结电容，因此实现了接合焊盘中的低寄生电容。 此外，导电块分别布置在轻掺杂区域和源/漏电极之间，以防止金属熔体丝线尖端接合。

公开(公告)号：US5760631A

公开(公告)日：1998-06-02

申请号：US685309

申请日：1996-07-23

申请人： Ta-Lee Yu ,  Ling-Yen Yeh

发明人： Ta-Lee Yu ,  Ling-Yen Yeh

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H03K19/003 ,  H03K19/0948 ,  G05F1/20

CPC分类号： H01L27/0251 ,  H01L27/0218 ,  H03K19/00315

摘要： A protection circuit for a CMOS integrated circuit which is biased with a first voltage and a second voltage includes a voltage divider, a voltage comparator, and a switch. The full level of the first voltage is higher than that of the second voltage. The voltage divider divides the first voltage to be compared with the second voltage in the voltage comparator. The switch is controlled by the voltage comparator. The switch isolates the CMOS integrated circuit from the first voltage when the first voltage is lower than the second voltage. Therefore, no forward bias current path exists in the CMOS integrated circuit even though the voltage levels of the first and second voltages reach their full levels at different times.

摘要翻译： 用于以第一电压和第二电压偏置的CMOS集成电路的保护电路包括分压器，电压比较器和开关。 第一电压的全部电平高于第二电压。 分压器将电压比较器中的第一电压与第二电压进行比较。 开关由电压比较器控制。 当第一电压低于第二电压时，开关将CMOS集成电路与第一电压隔离。 因此，即使第一和第二电压的电压电平在不同时间达到满量程，CMOS集成电路中也不存在正向偏置电流路径。

公开(公告)号：US5742085A

公开(公告)日：1998-04-21

申请号：US756173

申请日：1996-11-25

申请人： Ta-Lee Yu

发明人： Ta-Lee Yu

IPC分类号： H01L27/02 ,  H01L23/62

CPC分类号： H01L27/0262

摘要： A low-voltage trigger electrostatic discharge protection circuit with different layout structure, smaller chip area for better performance and space saving is connected, to the bonding pad of an IC to protect an internal circuit of an IC from electrostatic discharge damage using at least one NMOS transistor and at least two SCR connected in parallel between the bonding pad and a circuit ground point. When the electrostatic discharge stress is applied to the bonding pad, the NMOS will breakdown before breakdown of the gate oxide layer of the internal circuit to trigger the SCRs into snapback mode operation. Then the electrostatic discharge stress on the bonding pad is released by two SCRs (or more). Because the electrostatic discharge stress can be released by two SCRs at the same time, the invention can protect the SCRs from damage as well rather than the prior art using just one SCR and lead to better ESD performance. Furthermore, the chip area of the invention is about 150 .mu.m.sup.2 smaller than that of prior art for space saving. For more precise statement, the invention provides about 10% chip area saving.

摘要翻译： 具有不同布局结构的低电压触发器静电放电保护电路，将更小的芯片面积更好的性能和节省空间连接到IC的焊盘，以保护IC的内部电路免受静电放电损坏，使用至少一个NMOS 晶体管和至少两个SCR并联连接在焊盘和电路接地点之间。 当静电放电应力施加到接合焊盘时，NMOS将在内部电路的栅极氧化层击穿之前击穿，以将SCR触发成快速恢复模式操作。 然后通过两个SCR（或更多）释放焊盘上的静电放电应力。 因为静电放电应力可以同时由两个SCR释放，所以本发明可以保护SCR免受损坏，而不是使用仅一个SCR的现有技术来导致更好的ESD性能。 此外，本发明的芯片面积比现有技术的芯片面积小约150μm，以节省空间。 为了更准确的说明，本发明提供约10％的芯片面积节省。

公开(公告)号：US5705841A

公开(公告)日：1998-01-06

申请号：US851808

申请日：1997-05-06

申请人： Ta-Lee Yu

发明人： Ta-Lee Yu

IPC分类号： H01L27/02 ,  H01L23/62

CPC分类号： H01L27/0266

摘要： An electrostatic discharge (ESD) protection device includes a drain region and a source region, each having a heavily-doped region and a lightly-doped region, wherein the junction depth of the lightly-doped region is deeper than that of the heavily doped region. Accordingly, the ESD current density will be decreased owing to the enlarged junction area during the ESD event. In addition, the heat dissipation can be spread over the enlarged junction area instead of being focused on the cylindrical portion. Moreover, low parasitic capacitance in the bond pad is achieved because the junction capacitance of the lightly-doped region is smaller than that of the heavily-doped region. Furthermore, conducting blocks are arranged between the lightly-doped regions and the source/drain electrodes, respectively, to prevent the metal melt filament from spiking the junction.

摘要翻译： 静电放电（ESD）保护器件包括漏极区域和源极区域，每个区域具有重掺杂区域和轻掺杂区域，其中轻掺杂区域的结深度比重掺杂区域的深度深 。 因此，由于ESD事件期间扩大的接合面积，ESD电流密度将降低。 此外，散热可以扩大在扩大的接合面积上，而不是聚焦在圆柱形部分上。 此外，由于轻掺杂区域的结电容小于重掺杂区域的结电容，因此实现了接合焊盘中的低寄生电容。 此外，导电块分别布置在轻掺杂区域和源/漏电极之间，以防止金属熔体丝线尖端接合。