公开(公告)号：US5444014A

公开(公告)日：1995-08-22

申请号：US357021

申请日：1994-12-16

Applicant: Byung-Ryul Ryum ,  Tae-Hyeon Han ,  Soo-Min Lee ,  Deok-Ho Cho ,  Seong-Hearn Lee ,  Jin-Young Kang

Inventor： Byung-Ryul Ryum ,  Tae-Hyeon Han ,  Soo-Min Lee ,  Deok-Ho Cho ,  Seong-Hearn Lee ,  Jin-Young Kang

IPC: H01L21/331 ,  H01L21/762 ,  H01L21/76

CPC classification number: H01L29/66287 ,  H01L21/76264 ,  H01L21/76294 ,  H01L29/66265 ,  H01L21/76275 ,  H01L21/76283 ,  H01L21/76286 ,  Y10S148/012

Abstract: Disclosed is a method of fabricating an SOI substrate, comprising the steps of forming a first insulating layer on a single crystal silicon substrate; patterning the first insulating layer to form an opening; growing a single crystal silicon in the opening to form active and inactive regions; polishing the active region 31 as the first insulating layer as a polishing stopper to form a planarized surface; depositing a second insulating layer on the planarized surface; bonding a bonding substrate to the second insulating layer; and polishing the silicon substrate using the first insulating layer as a stopper up to a surface of the active region. By the method, a stray capacitance occurring between an SOI substrate and a metal wiring portion formed thereon can be significantly reduced owing to a relatively thick insulating layer therebetween, and a parasitic capacitance can be eliminated owing to an insulating layer interposed between a bonding substrate and an active region to be used as a buried collector.

Abstract translation: 公开了一种制造SOI衬底的方法，包括以下步骤：在单晶硅衬底上形成第一绝缘层; 图案化第一绝缘层以形成开口; 在开口中生长单晶硅以形成活性和非活性区域; 将作为第一绝缘层的有源区域31抛光为抛光停止层以形成平坦化表面; 在平坦化表面上沉积第二绝缘层; 将接合基板接合到所述第二绝缘层; 以及使用所述第一绝缘层作为阻挡物直到所述有源区的表面来研磨所述硅衬底。 通过该方法，由于SOI衬底和形成在其上的金属布线部分之间的寄生电容由于其之间的相对较厚的绝缘层而可以显着降低，并且由于绝缘层介于接合衬底和 用作埋藏式收集器的有源区域。

公开(公告)号：US5981345A

公开(公告)日：1999-11-09

申请号：US891013

申请日：1997-07-10

Applicant: Byung-Ryul Ryum ,  Soo-Min Lee ,  Deok-Ho Cho ,  Tae-Hyeon Han

Inventor： Byung-Ryul Ryum ,  Soo-Min Lee ,  Deok-Ho Cho ,  Tae-Hyeon Han

IPC: H01L27/06 ,  H01L21/336 ,  H01L29/10 ,  H01L29/417 ,  H01L29/45 ,  H01L21/249

CPC classification number: H01L29/66477 ,  H01L29/1054 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/66651

Abstract: The present invention relates to a metal silicon field effect transistor (MOSFET), and more particularly to a MOSFET, using a Si or SiGe channel to effectively adjust threshold voltage. The transistor according to the present invention can solve the problems, such as the punch-through caused by the short distance between the source region and the drain region, the decrease of the breakdown voltage between the source region and the drain region and the leakage current flowing into the bulk region beneath the channel due to the drain-induced barrier lowering. Furthermore, because the source region and the drain region are isolated from the semiconductor substrate by the lower insulation layer, the removal of the parasite junction capacitor speed up the transistor.

公开(公告)号：US5962879A

公开(公告)日：1999-10-05

申请号：US854665

申请日：1997-05-12

Applicant: Byung-Ryul Ryum ,  Deok-Ho Cho ,  Tae-Hyeon Han ,  Soo-Min Lee ,  Kwang-Eui Pyun

Inventor： Byung-Ryul Ryum ,  Deok-Ho Cho ,  Tae-Hyeon Han ,  Soo-Min Lee ,  Kwang-Eui Pyun

IPC: H01L21/331 ,  H01L29/737

CPC classification number: H01L29/66242 ,  H01L29/7378

Abstract: The invention relates to a method for manufacturing a super self-aligned heterojunction bipolar transistor which is capable of miniaturizing an element, simplifying the process step thereof by employing a selective collector epitaxial growth process without using a trench for isolating between elements. According to the invention, isolation between elements is derived by using a mask defining an emitter region and a second spacer. The base layer has multi-layer structure being made of a Si, an undoped SiGe, a SiGe doped a p-type impurity in-situ and Si. Also, the selective epitaxial growth for a base is not required. Thus, it can be less prone to a flow of leakage current or an emitter-base-collector short effect.

Abstract translation: 本发明涉及一种用于制造能够使元件小型化的超自对准异质结双极晶体管的方法，通过采用选择性集电体外延生长工艺简化其工艺步骤，而不使用用于元件间隔离的沟槽。 根据本发明，通过使用限定发射极区域和第二间隔物的掩模来导出元件之间的隔离。 基层具有由Si，未掺杂的SiGe，SiGe原位掺杂p型杂质的Si和Si构成的多层结构。 此外，不需要基底的选择性外延生长。 因此，可能不太容易发生漏电流或发射极 - 基极 - 集电极短路效应。

公开(公告)号：US5897359A

公开(公告)日：1999-04-27

申请号：US987474

申请日：1997-12-09

Applicant: Deok Ho Cho ,  Soo Min Lee ,  Tae Hyeon Han ,  Byung Ryul Ryum ,  Kwang Eui Pyun

Inventor： Deok Ho Cho ,  Soo Min Lee ,  Tae Hyeon Han ,  Byung Ryul Ryum ,  Kwang Eui Pyun

IPC: H01L29/74 ,  H01L21/331 ,  H01L29/737 ,  H01L21/8222

CPC classification number: H01L29/66242 ,  H01L29/7378

Abstract: There is disclosed a method of manufacturing a silicon/silicon germanium heterojunction bipolar transistor having a good conformity and an improved speed characteristic, which includes the steps of sequentially laminating an underlying nitride film, an oxide film, a polycrystalline silicon film and an upper nitride on a semiconductor substrate on which devices are separated and a collector is formed; sequentially etching said upper nitride film and said polycrystalline silicon film using the emitter as a mask, and then forming a side wall nitride film; selectively wet-etching said oxide film to form a side base linker opening; burying said base linker opening with a polycrystalline silicon; oxidizing said polycrystalline silicon film buried into said base linker opening and then removing said oxide film by means of the selective wet-etch process; removing said upper nitride and then forming a silicon/silicon germanium film as a base film on the exposed thereof; and forming an emitter said silicon/silicon germanium film.

Abstract translation: 公开了一种制造具有良好一致性和改进的速度特性的硅/硅锗异质结双极晶体管的方法，其包括以下步骤：将下面的氮化物膜，氧化物膜，多晶硅膜和上部氮化物依次层压在 半导体衬底，器件分离并形成集电极; 使用发射极作为掩模，依次蚀刻所述上部氮化物膜和所述多晶硅膜，然后形成侧壁氮化物膜; 选择性地湿蚀刻所述氧化膜以形成侧基连接器开口; 用多晶硅掩埋所述基底连接器开口; 氧化所述多晶硅膜，所述多晶硅膜埋入所述基底连接器开口中，然后通过选择性湿蚀刻工艺除去所述氧化物膜; 去除所述上部氮化物，然后在其暴露时形成硅/硅锗膜作为基膜; 以及形成所述硅/硅锗膜的发射极。

公开(公告)号：US5459084A

公开(公告)日：1995-10-17

申请号：US358533

申请日：1994-12-19

Applicant: Byung-Ryul Ryum ,  Deok-Ho Cho ,  Tae-Hyeon Han ,  Soo-Min Lee ,  Oh-Joon Kwon

Inventor： Byung-Ryul Ryum ,  Deok-Ho Cho ,  Tae-Hyeon Han ,  Soo-Min Lee ,  Oh-Joon Kwon

IPC: H01L21/331 ,  H01L29/737 ,  H01L21/265

CPC classification number: H01L29/66242 ,  H01L29/7378 ,  Y10S148/01 ,  Y10S148/011 ,  Y10S148/072

Abstract: Disclosed is a fabrication of a hetero-junction bipolar transistor in which a base parasitic capacitance is fully reduced by using a metallic silicide as a base, comprising the steps of injecting an impurity in a silicon substrate to form a conductive buried collector region; growing a collector epitaxial layer on the buried collector region and forming a field oxide layer; selectively injecting an impurity into the collector epitaxial layer to form a collector sinker; sequentially forming a base layer and an first oxide layer thereon; patterning the first oxide layer to define an extrinsic base region; ion-implanting an impurity in the extrinsic base region using a patterned oxide layer as a mask and removing the patterned oxide layer; depositing a metallic silicide film thereon to form a base electrode thin film; forming a capping oxide layer of about 500 .ANG. thickness only on the base electrode thin film; forming an isolating oxide layer thereon and sequentially and selectively removing the isolating oxide layer, the capping oxide layer, the base electrode thin film and the base layer using a patterned photomask to form a pattern, the isolating oxide layer being provided to electrically isolate base and emitter; forming a side wall oxide layer at both side edges of the pattern; removing a portion of the isolating oxide layer to define an emitter region; forming a passivation layer thereon and selectively removing the passivation layer to form contact holes; and depositing a polysilicon layer doped with impurity ions in the contact holes to form electrodes.

Abstract translation: 公开了通过使用金属硅化物作为基底而使基极寄生电容完全降低的异质结双极晶体管的制造方法，包括以下步骤：在硅衬底中注入杂质以形成导电的埋地集电区; 在掩埋的集电极区上生长集电极外延层并形成场氧化物层; 选择性地将杂质注入到集电极外延层中以形成集电极沉降片; 在其上依次形成基底层和第一氧化物层; 图案化第一氧化物层以限定外部碱性区域; 使用图案化氧化物层作为掩模在外部基极区域中离子注入杂质并除去图案化的氧化物层; 在其上沉积金属硅化物膜以形成基极薄膜; 仅在基极薄膜上形成约500厚度的覆盖氧化物层; 在其上形成隔离氧化物层，并使用图案化的光掩模依次选择性地去除隔离氧化物层，封盖氧化物层，基极薄膜和基层，形成图案，隔离氧化物层被提供以电隔离基极和 发射器 在图案的两个侧边缘处形成侧壁氧化物层; 去除所述隔离氧化物层的一部分以限定发射极区域; 在其上形成钝化层并选择性地去除钝化层以形成接触孔; 以及在所述接触孔中沉积掺杂有杂质离子的多晶硅层以形成电极。

公开(公告)号：US06552374B2

公开(公告)日：2003-04-22

申请号：US09765499

申请日：2001-01-17

Applicant: Tae-Hyeon Han ,  Byung Ryul Ryum ,  Soo-Min Lee ,  Deok-Ho Cho

Inventor： Tae-Hyeon Han ,  Byung Ryul Ryum ,  Soo-Min Lee ,  Deok-Ho Cho

IPC: H01L31072

CPC classification number: H01L29/66287 ,  H01L29/7322

Abstract: Disclosed are a method for forming a base layer by epitaxial growth technology of a heterojunction bipolar device and a structure of the bipolar device manufactured by the method. The method comprises steps of depositing an insulation film containing silicon nitride on a substrate and removing a part of the insulation film to define a collector area; growing a first semiconductor in the collector area by selective epitaxial growth method to form the collector protruded over the insulation film in the form of a mushroom; forming an oxide film containing silicon dioxide on a surface of the collector protruded over the silicon nitride; selectively growing a second polycrystalline semiconductor material on only the nitride insulation film at the same height as the protruded portion of the collector to form a first base semiconductor electrode; removing an upper surface of the oxide film to expose the collector; and growing a second semiconductor containing silicon-germanium on the second polycrystalline semiconductor and the collector of the first semiconductor to form a second base semiconductor electrode on the first base semiconductor electrode and the base on the collector, thereby preventing a current leakage and a loading effect.

公开(公告)号：US06362066B1

公开(公告)日：2002-03-26

申请号：US09469395

申请日：1999-12-22

Applicant: Byung Ryul Ryum ,  Tae Hyeon Han ,  Soo Min Lee ,  Deok Ho Cho

Inventor： Byung Ryul Ryum ,  Tae Hyeon Han ,  Soo Min Lee ,  Deok Ho Cho

IPC: H01L21331

CPC classification number: H01L29/66287 ,  H01L29/66242

Abstract: The present invention is related to a bipolar transistor in which the in-situ doped epitaxial Si or SiGe base layer is used instead of using an ion-implanted Si base, in order to achieve higher cutoff frequency. The SiGe base having the narrower energy bandgap than the Si emitter allows to enhance the current gain, the cutoff frequency (fT), and the maximum oscillation frequency (fmax). The narrow bandgap SiGe base also allows to have higher base doping concentration. As a result, the intrinsic base resistance is lowered and the noise figure is thus lowered. Parasitic base resistance is also minimized by using a metallic silicide base ohmic electrode. The present invention is focused on low cost, high repeatability and reliability by simplifying the manufacturing process step.

Abstract translation: 本发明涉及一种双极晶体管，其中使用原位掺杂的外延Si或SiGe基层代替使用离子注入的Si基，以便实现更高的截止频率。 具有比Si发射器更窄的能带隙的SiGe基极允许增强电流增益，截止频率（fT）和最大振荡频率（fmax）。 窄带隙SiGe基极还允许具有较高的基极掺杂浓度。 结果，本征基极电阻降低，噪声系数降低。 通过使用金属硅化物基极欧姆电极也使寄生基极电阻最小化。 通过简化制造工艺步骤，本发明集中在低成本，高重复性和可靠性上。

公开(公告)号：US06190984B1

公开(公告)日：2001-02-20

申请号：US09229831

申请日：1999-01-13

Applicant: Byung-Ryul Ryum ,  Deok-Ho Cho ,  Tae-Hyeon Han ,  Soo-Min Lee ,  Kwang-Eui Pyun

Inventor： Byung-Ryul Ryum ,  Deok-Ho Cho ,  Tae-Hyeon Han ,  Soo-Min Lee ,  Kwang-Eui Pyun

IPC: H01L218222

CPC classification number: H01L29/66242

Abstract: The invention relates to a method for manufacturing a super self-aligned heterojunction bipolar transistor which is capable of miniaturizing an element, simplifying the process step thereof by employing a selective collector epitaxial growth process without using a trench for isolating between elements. According to the invention, isolation between elements is derived by using a mask defining an emitter region and a second spacer. The base layer has multi-layer structure being made of a Si, an undoped SiGe, a SiGe doped a p-type impurity in-situ and Si. Also, the selective epitaxial growth for a base is not required. Thus, it can be less prone to a flow of leakage current or an emitter-base-collector short effect.

Abstract translation: 本发明涉及一种用于制造能够使元件小型化的超自对准异质结双极晶体管的方法，通过采用选择性集电体外延生长工艺简化其工艺步骤，而不使用用于元件间隔离的沟槽。 根据本发明，通过使用限定发射极区域和第二间隔物的掩模来导出元件之间的隔离。 基层具有由Si，未掺杂的SiGe，SiGe原位掺杂p型杂质的Si和Si构成的多层结构。 此外，不需要基底的选择性外延生长。 因此，可能不太容易发生漏电流或发射极 - 基极 - 集电极短路效应。

公开(公告)号：US5696020A

公开(公告)日：1997-12-09

申请号：US470479

申请日：1995-06-05

Applicant: Byung-Ryul Ryum ,  Tae-Hyeon Han ,  Soo-Min Lee ,  Deok-Ho Cho ,  Jin-Young Kang

Inventor： Byung-Ryul Ryum ,  Tae-Hyeon Han ,  Soo-Min Lee ,  Deok-Ho Cho ,  Jin-Young Kang

IPC: H01L21/762 ,  H01L21/76

CPC classification number: H01L21/76224 ,  H01L21/76202

Abstract: Disclosed is a device isolating method of a semiconductor device, comprising the steps of sequentially forming a pad oxide film, a polysilicon film and an insulating layer, on a silicon substrate, said insulating layer being composed of a first silicon oxide film, a nitride film and a second silicon oxide film formed sequentially on the polysilicon film; defining active and inactive regions by using a patterned photomask; removing the insulating layer only on the inactive region so as to expose a surface of the polysilicon film; forming a side wall at both edges of the insulating layer on the active region, said side wall being composed of a nitride film; depositing a third silicon oxide film on the surface of the polysilicon film; removing the side wall and etching the substrate to a predetermined depth to form a trench; filling an insulating material into the trench and depositing it up to the second silicon oxide so as to form an insulating film for isolating; simultaneously removing the second silicon oxide film and the silicon oxide film and removing the polysilicon film only the inactive region; performing a thermal oxidation to form a field oxide film on the inactive region; and sequentially removing the isolating layer and the polysilicon film formed on the active region. Because the active region is defined using an insulator-filled shallow trench before performing thermal oxidation, no oxygen is penetrated into the active region during the thermal oxidation, whereby a field oxide film can be formed without occurrence of a Bird's beak.

Abstract translation: 公开了一种半导体器件的器件隔离方法，包括以下步骤：在硅衬底上顺序形成衬垫氧化膜，多晶硅膜和绝缘层，所述绝缘层由第一氧化硅膜，氮化膜 以及顺序地形成在所述多晶硅膜上的第二氧化硅膜; 通过使用图案化的光掩模来定义有源和非活性区域; 仅在非活性区域上去除绝缘层，以暴露多晶硅膜的表面; 在有源区域上的绝缘层的两个边缘处形成侧壁，所述侧壁由氮化物膜构成; 在所述多晶硅膜的表面上沉积第三氧化硅膜; 去除侧壁并将衬底蚀刻到预定深度以形成沟槽; 将绝缘材料填充到沟槽中并将其沉积到第二氧化硅上，以形成用于隔离的绝缘膜; 同时去除第二氧化硅膜和氧化硅膜，并且仅去除多晶硅膜的非活性区域; 进行热氧化以在非活性区域上形成场氧化物膜; 并依次去除形成在有源区上的隔离层和多晶硅膜。 由于在进行热氧化之前使用绝缘子填充的浅沟槽限定有源区域，所以在热氧化期间没有氧气渗透到有源区域中，由此可以形成场氧化膜而不发生鸟喙。

公开(公告)号：US5668022A

公开(公告)日：1997-09-16

申请号：US700930

申请日：1996-08-23

Applicant: Deok-Ho Cho ,  Soo-Min Lee ,  Tae-Hyeon Han ,  Byung-Ryul Ryum ,  Kwang-Eui Pyun

Inventor： Deok-Ho Cho ,  Soo-Min Lee ,  Tae-Hyeon Han ,  Byung-Ryul Ryum ,  Kwang-Eui Pyun

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/165 ,  H01L29/732 ,  H01L29/737 ,  H01L21/265

CPC classification number: H01L29/66242 ,  H01L29/7378 ,  Y10S148/072

Abstract: A silicon/silicon-germanium bipolar transistor fabrication method employs a metallic silicide film as an extrinsic base electrode to reduce resistance of the extrinsic base electrode, and to increase a maximum oscillation frequency and cut-off frequency due to its self-aligned structure. The fabrication method enables agglomeration to occur on the side wall of the polycrystalline silicon film connected to the metallic silicide film instead of on the interface between the metallic silicide film and the lower silicon/silicon-germanium film, and leads the extrinsic base electrode to be sandwitched by the insulator films, thereby realizing a constant resistance and also resulting in the application of integrated circuits to a mass production mechanism.

Abstract translation: 硅/硅 - 锗双极晶体管制造方法使用金属硅化物膜作为外部基极，以降低外部基极的电阻，并且由于其自对准结构而增加最大振荡频率和截止频率。 该制造方法可以在连接到金属硅化物膜的多晶硅膜的侧壁上而不是在金属硅化物膜和下硅/硅 - 锗膜之间的界面上发生聚集，并且引导外部基极为 由绝缘体膜切割，从而实现恒定的电阻，并且还导致集成电路应用于大规模生产机构。