公开(公告)号：US07696738B2

公开(公告)日：2010-04-13

申请号：US11898690

申请日：2007-09-14

申请人： Toshihiko Kasai ,  Masatoshi Kokubun ,  Kenji Kato

发明人： Toshihiko Kasai ,  Masatoshi Kokubun ,  Kenji Kato

IPC分类号： G05F1/575

CPC分类号： H02M3/1588 ,  H02M2001/0032 ,  Y02B70/1466 ,  Y02B70/16

摘要： A DC-DC converter reducing reversed current in a low load state and increasing output voltage response speed. An error amplification circuit generates an error signal from the output voltage. A pulse signal generation circuit generates a first pulse signal in accordance with the error signal. A comparison circuit generates a comparison result signal from the error signal. A drive signal generation circuit generates a constant level signal and a second pulse signal. An output circuit receives the first pulse signal and either the constant level signal or the second pulse signal to generate first and second drive signals for driving first and second transistors. The output circuit generates the second drive signal in accordance with the first pulse signal when receiving the constant level signal and generates the second drive signal with the first and second pulse signals when receiving the second pulse signal.

摘要翻译： DC-DC转换器在低负载状态下降低反向电流并提高输出电压响应速度。 误差放大电路从输出电压产生误差信号。 脉冲信号发生电路根据误差信号产生第一脉冲信号。 比较电路产生来自误差信号的比较结果信号。 驱动信号发生电路产生恒定电平信号和第二脉冲信号。 输出电路接收第一脉冲信号和恒定电平信号或第二脉冲信号，以产生用于驱动第一和第二晶体管的第一和第二驱动信号。 当接收到恒定电平信号时，输出电路根据第一脉冲信号产生第二驱动信号，并在接收到第二脉冲信号时产生具有第一和第二脉冲信号的第二驱动信号。

公开(公告)号：US20080252369A1

公开(公告)日：2008-10-16

申请号：US12000995

申请日：2007-12-19

申请人： Toshihiko Kasai ,  Shinya Udo ,  Masatoshi Kokubun ,  Yoshihiro Kizaki

发明人： Toshihiko Kasai ,  Shinya Udo ,  Masatoshi Kokubun ,  Yoshihiro Kizaki

IPC分类号： H03F1/30

CPC分类号： H03F3/45753 ,  G09G3/3688

摘要： An operational amplifier capable of offset cancel in a shorter period, as well as a line driver capable of shortening one horizontal period and a liquid crystal display device are provided. In the operational amplifier of the invention, a time necessary for feed back control can be shortened than usual by a constitution that an output voltage VO in one horizontal period H1 which is one horizontal period before is defined as a reference voltage in an offset cancel preparatory period HC2, thereby changing the output voltage VO(2) only by the offset voltage VO(2) by the feed back control. In the line driver of the invention, the operational amplifier not used for the output of display data D1 to D6 conducts offset cancel operation and it is successively shifted on every one horizontal period. Since it is no more necessary to incorporate the offset cancel preparatory period in the output period, one horizontal period can be shortened further.

公开(公告)号：US20080067989A1

公开(公告)日：2008-03-20

申请号：US11898690

申请日：2007-09-14

申请人： Toshihiko Kasai ,  Masatoshi Kokubun ,  Kenji Kato

发明人： Toshihiko Kasai ,  Masatoshi Kokubun ,  Kenji Kato

IPC分类号： G05F1/44

CPC分类号： H02M3/1588 ,  H02M2001/0032 ,  Y02B70/1466 ,  Y02B70/16

摘要： A DC-DC converter reducing reversed current in a low load state and increasing output voltage response speed. An error amplification circuit generates an error signal from the output voltage. A pulse signal generation circuit generates a first pulse signal in accordance with the error signal. A comparison circuit generates a comparison result signal from the error signal. A drive signal generation circuit generates a constant level signal and a second pulse signal. An output circuit receives the first pulse signal and either the constant level signal or the second pulse signal to generate first and second drive signals for driving first and second transistors. The output circuit generates the second drive signal in accordance with the first pulse signal when receiving the constant level signal and generates the second drive signal with the first and second pulse signals when receiving the second pulse signal.

摘要翻译： DC-DC转换器在低负载状态下降低反向电流并提高输出电压响应速度。 误差放大电路从输出电压产生误差信号。 脉冲信号发生电路根据误差信号产生第一脉冲信号。 比较电路产生来自误差信号的比较结果信号。 驱动信号发生电路产生恒定电平信号和第二脉冲信号。 输出电路接收第一脉冲信号和恒定电平信号或第二脉冲信号，以产生用于驱动第一和第二晶体管的第一和第二驱动信号。 当接收到恒定电平信号时，输出电路根据第一脉冲信号产生第二驱动信号，并在接收到第二脉冲信号时产生具有第一和第二脉冲信号的第二驱动信号。

公开(公告)号：US20070132435A1

公开(公告)日：2007-06-14

申请号：US11362513

申请日：2006-02-27

申请人： Morihito Hasegawa ,  Hidekiyo Ozawa ,  Shoji Tajiri ,  Toshihiko Kasai

发明人： Morihito Hasegawa ,  Hidekiyo Ozawa ,  Shoji Tajiri ,  Toshihiko Kasai

IPC分类号： G05F1/00

CPC分类号： H02M1/36 ,  H02M3/156 ,  H02M2003/078 ,  H03K17/302 ,  H03K2217/0018

摘要： The invention provides a DC-DC converter capable of being started up in a state in which an input voltage is low and capable of being structured without increasing a circuit size. A back-gate voltage (Vsb) is outputted from a back-gate voltage generating circuit (VBGN), and is inputted to a back gate of a transistor (FET1). During a period during which an output voltage (Vout) is lower than a reference voltage (e0), an oscillation signal (OS1) is inputted to a gate of the transistor (FET1), and the back-gate voltage (Vsb) is set at a grounded voltage. Therefore, the transistor (FET1) has a reference threshold voltage (Vto). On the other hand, during a period during which the output voltage (Vout) is higher than the reference voltage (e0), a pulse signal (PS) is inputted to the gate of the transistor (FET1), and the back-gate voltage (Vsb) is set at an output voltage of a charge pump portion (5). Therefore, the transistor (FET1) has a threshold voltage higher than the reference threshold voltage (Vto).

摘要翻译： 本发明提供一种DC-DC转换器，其能够在输入电压低的状态下启动并且能够在不增加电路尺寸的情况下被构造。 背栅电压（Vsb）从背栅极电压产生电路（VBGN）输出，并被输入到晶体管（FET1）的背栅极。 在输出电压（Vout）低于基准电压（e 0）的期间，将振荡信号（OS1）输入到晶体管（FET1）的栅极，将栅极电压（Vsb ）设置在接地电压。 因此，晶体管（FET1）具有参考阈值电压（Vto）。 另一方面，在输出电压（Vout）高于基准电压（e 0）的期间，将脉冲信号（PS）输入到晶体管（FET1）的栅极， 栅极电压（Vsb）设定在电荷泵部（5）的输出电压。 因此，晶体管（FET1）具有高于参考阈值电压（Vto）的阈值电压。

公开(公告)号：US07025702B2

公开(公告)日：2006-04-11

申请号：US10741007

申请日：2003-12-19

申请人： Masahiro Saito ,  Kunihiro Osawa ,  Toshihiko Kasai

发明人： Masahiro Saito ,  Kunihiro Osawa ,  Toshihiko Kasai

IPC分类号： F16H57/04

CPC分类号： F16H57/0483 ,  F16H48/08 ,  F16H48/40 ,  F16H57/0482 ,  F16H2048/085 ,  F16H2048/387

摘要： A differential capable of satisfying a demand for an improvement in performance and a reduction in cost in which the pinion shaft 19 is movably disposed in the differential case 2, and sliding bearings 16, 41, 42 are disposed between mutually opposite surfaces of the pair of side gears 13 and the differential case 2 and between mutually opposite surfaces of the pinions 12 and the differential case 2, respectively.

摘要翻译： 能够满足对性能的提高的需求的差速器和小齿轮轴19可移动地设置在差速器壳体2中的成本降低，并且滑动轴承16,41,42设置在该对的相互相对的表面之间 侧齿轮13和差速器壳体2以及小齿轮12和差速器壳体2的相互相对的表面之间。

公开(公告)号：US06940338B2

公开(公告)日：2005-09-06

申请号：US10706664

申请日：2003-11-12

申请人： Yoshihiro Kizaki ,  Osamu Kudo ,  Shinya Udo ,  Toshihiko Kasai

发明人： Yoshihiro Kizaki ,  Osamu Kudo ,  Shinya Udo ,  Toshihiko Kasai

IPC分类号： H03K19/00 ,  G05F3/30 ,  H01L27/00 ,  H03F3/343 ,  G05F1/10

CPC分类号： G05F3/30

摘要： A bias circuit generates a first voltage at a first node. A second current source generates, according to the first voltage, a power supply current to be supplied to an internal circuit including transistors. A correcting transistor in a correcting circuit supplies the first node with a correcting current generated according to a constant voltage. Because of this, the first voltage is adjusted according to the correcting current. Therefore, the operating speed of the internal circuit is prevented from changing, being dependent on the variation of the threshold voltage and temperature variation of a transistor. As a result, the yield can be improved, independently of the variation of the threshold voltage among semiconductor integrated circuit chips, which occurs in a fabrication process. Further, temperature dependency of the operating speed of the internal circuit can be reduced, which can improve the yield of the semiconductor integrated circuit.

摘要翻译： 偏置电路在第一节点处产生第一电压。 第二电流源根据第一电压产生要提供给包括晶体管的内部电路的电源电流。 校正电路中的校正晶体管向第一节点提供根据恒定电压产生的校正电流。 因此，根据校正电流来调整第一电压。 因此，防止内部电路的工作速度发生变化，这取决于晶体管的阈值电压和温度变化的变化。 结果，与制造过程中发生的半导体集成电路芯片之间的阈值电压的变化无关，可以提高产量。 此外，可以降低内部电路的工作速度的温度依赖性，这可以提高半导体集成电路的产量。

公开(公告)号：US08476881B2

公开(公告)日：2013-07-02

申请号：US12778812

申请日：2010-05-12

申请人： Toshihiko Kasai ,  Hidenobu Ito

发明人： Toshihiko Kasai ,  Hidenobu Ito

IPC分类号： G05F1/10 ,  G05F1/652 ,  G05F1/44

摘要： A power control device for performing switching control for an output voltage of a power supply device includes a signal generation circuit for comparing a difference between a value of the output voltage and a value of a first reference voltage with a value of a second reference voltage, and for stopping the switching control when a value of the difference is less than or equal to the value of the second reference voltage, and an adjuster circuit for adjusting the second reference voltage based on a ratio between a value of an input voltage and the value of the output voltage.

公开(公告)号：US07880537B2

公开(公告)日：2011-02-01

申请号：US12000995

申请日：2007-12-19

申请人： Toshihiko Kasai ,  Shinya Udo ,  Masatoshi Kokubun ,  Yoshihiro Kizaki

发明人： Toshihiko Kasai ,  Shinya Udo ,  Masatoshi Kokubun ,  Yoshihiro Kizaki

IPC分类号： H03F1/02

CPC分类号： H03F3/45753 ,  G09G3/3688

摘要： An operational amplifier capable of offset cancel in a shorter period, as well as a line driver capable of shortening one horizontal period and a liquid crystal display device are provided. In the operational amplifier of the invention, a time necessary for feed back control can be shortened than usual by a constitution that an output voltage VO in one horizontal period H1 which is one horizontal period before is defined as a reference voltage in an offset cancel preparatory period HC2, thereby changing the output voltage VO(2) only by the offset voltage VO(2) by the feed back control. In the line driver of the invention, the operational amplifier not used for the output of display data D1 to D6 conducts offset cancel operation and it is successively shifted on every one horizontal period. Since it is no more necessary to incorporate the offset cancel preparatory period in the output period, one horizontal period can be shortened further.

摘要翻译： 提供能够在较短时间内抵消抵消的运算放大器以及能够缩短一个水平周期的线路驱动器和液晶显示装置。 在本发明的运算放大器中，通过将一个水平周期的一个水平周期H1的输出电压VO定义为偏移消除准备中的基准电压的结构，可以缩短反馈控制所需的时间 从而通过反馈控制仅偏移电压VO（2）来改变输出电压VO（2）。 在本发明的线路驱动器中，未用于显示数据D1至D6的输出的运算放大器进行偏移消除操作，并且每隔一个水平周期依次移位。 由于不需要在偏移消除准备期间中包含输出期间，所以可以进一步缩短一个水平周期。

公开(公告)号：US20090201618A1

公开(公告)日：2009-08-13

申请号：US12369907

申请日：2009-02-12

申请人： Morihito Hasegawa ,  Hidenobu Ito ,  Kwok Fai Hui ,  Toshihiko Kasai ,  Katsuyuki Yasukouchi

发明人： Morihito Hasegawa ,  Hidenobu Ito ,  Kwok Fai Hui ,  Toshihiko Kasai ,  Katsuyuki Yasukouchi

IPC分类号： H02H9/08

CPC分类号： G05F1/573 ,  H03K17/0822

摘要： A power supply circuit includes an output transistor including a source coupled to power supply voltage, and a drain from which output voltage is outputted; a first error amplifier powered by the power supply voltage and outputting a signal based on a potential difference between the output voltage and a reference voltage; a buffer transistor including a gate coupled to the output of the first error amplifier, and a source coupled via a constant current source to the power supply voltage and coupled to a gate of the output transistor; a current detection transistor coupled to the output transistor such that a gate and source are shared; and an overcurrent protection circuit configured to limit the drain current of the buffer transistor based on the increase of the drain current of the current detection transistor and thereby control the output current of the output transistor.

摘要翻译： 电源电路包括：输出晶体管，其包括耦合到电源电压的源极和从其输出输出电压的漏极; 由所述电源电压供电的第一误差放大器，并且基于所述输出电压和参考电压之间的电位差输出信号; 缓冲晶体管，其包括耦合到所述第一误差放大器的输出的栅极，以及经由恒定电流源耦合到所述电源电压并耦合到所述输出晶体管的栅极的源极; 耦合到输出晶体管的电流检测晶体管，使得门和源被共享; 以及过电流保护电路，其被配置为基于电流检测晶体管的漏极电流的增加来限制缓冲晶体管的漏极电流，从而控制输出晶体管的输出电流。

公开(公告)号：US07298117B2

公开(公告)日：2007-11-20

申请号：US11362513

申请日：2006-02-27

申请人： Morihito Hasegawa ,  Hidekiyo Ozawa ,  Shoji Tajiri ,  Toshihiko Kasai

发明人： Morihito Hasegawa ,  Hidekiyo Ozawa ,  Shoji Tajiri ,  Toshihiko Kasai

IPC分类号： G05F1/10

CPC分类号： H02M1/36 ,  H02M3/156 ,  H02M2003/078 ,  H03K17/302 ,  H03K2217/0018

摘要： The invention provides a DC-DC converter capable of being started up in a state in which an input voltage is low and capable of being structured without increasing a circuit size. A back-gate voltage (Vsb) is outputted from a back-gate voltage generating circuit (VBGN), and is inputted to a back gate of a transistor (FET1). During a period during which an output voltage (Vout) is lower than a reference voltage (e0), an oscillation signal (OS1) is inputted to a gate of the transistor (FET1), and the back-gate voltage (Vsb) is set at a grounded voltage. Therefore, the transistor (FET1) has a reference threshold voltage (Vto). On the other hand, during a period during which the output voltage (Vout) is higher than the reference voltage (e0), a pulse signal (PS) is inputted to the gate of the transistor (FET1), and the back-gate voltage (Vsb) is set at an output voltage of a charge pump portion (5). Therefore, the transistor (FET1) has a threshold voltage higher than the reference threshold voltage (Vto).

摘要翻译： 本发明提供一种DC-DC转换器，其能够在输入电压低的状态下启动并且能够在不增加电路尺寸的情况下被构造。 背栅电压（Vsb）从背栅极电压产生电路（VBGN）输出，并被输入到晶体管（FET1）的背栅极。 在输出电压（Vout）低于基准电压（e 0）的期间，将振荡信号（OS1）输入到晶体管（FET1）的栅极，将栅极电压（Vsb ）设置在接地电压。 因此，晶体管（FET1）具有参考阈值电压（Vto）。 另一方面，在输出电压（Vout）高于基准电压（e 0）的期间，将脉冲信号（PS）输入到晶体管（FET1）的栅极， 栅极电压（Vsb）设定在电荷泵部（5）的输出电压。 因此，晶体管（FET1）具有高于参考阈值电压（Vto）的阈值电压。