公开(公告)号：US06940338B2

公开(公告)日：2005-09-06

申请号：US10706664

申请日：2003-11-12

申请人： Yoshihiro Kizaki ,  Osamu Kudo ,  Shinya Udo ,  Toshihiko Kasai

发明人： Yoshihiro Kizaki ,  Osamu Kudo ,  Shinya Udo ,  Toshihiko Kasai

IPC分类号： H03K19/00 ,  G05F3/30 ,  H01L27/00 ,  H03F3/343 ,  G05F1/10

CPC分类号： G05F3/30

摘要： A bias circuit generates a first voltage at a first node. A second current source generates, according to the first voltage, a power supply current to be supplied to an internal circuit including transistors. A correcting transistor in a correcting circuit supplies the first node with a correcting current generated according to a constant voltage. Because of this, the first voltage is adjusted according to the correcting current. Therefore, the operating speed of the internal circuit is prevented from changing, being dependent on the variation of the threshold voltage and temperature variation of a transistor. As a result, the yield can be improved, independently of the variation of the threshold voltage among semiconductor integrated circuit chips, which occurs in a fabrication process. Further, temperature dependency of the operating speed of the internal circuit can be reduced, which can improve the yield of the semiconductor integrated circuit.

摘要翻译： 偏置电路在第一节点处产生第一电压。 第二电流源根据第一电压产生要提供给包括晶体管的内部电路的电源电流。 校正电路中的校正晶体管向第一节点提供根据恒定电压产生的校正电流。 因此，根据校正电流来调整第一电压。 因此，防止内部电路的工作速度发生变化，这取决于晶体管的阈值电压和温度变化的变化。 结果，与制造过程中发生的半导体集成电路芯片之间的阈值电压的变化无关，可以提高产量。 此外，可以降低内部电路的工作速度的温度依赖性，这可以提高半导体集成电路的产量。

公开(公告)号：US07268763B2

公开(公告)日：2007-09-11

申请号：US10701856

申请日：2003-11-05

申请人： Hideto Fukuda ,  Shinya Udo ,  Masao Kumagai ,  Osamu Kudo

发明人： Hideto Fukuda ,  Shinya Udo ,  Masao Kumagai ,  Osamu Kudo

IPC分类号： G09G3/36

CPC分类号： G09G3/2011 ,  G09G3/20 ,  G09G3/3614 ,  G09G3/3688 ,  G09G3/3696 ,  G09G2310/027 ,  G09G2310/0297 ,  H03M1/069 ,  H03M1/687 ,  H03M1/76 ,  H03M1/765

摘要： A drive circuit of a display that decreases the number of gates in a selection circuit to reduce chip area. The drive circuit includes a first voltage dividing circuit for generating a plurality of divisional voltages by dividing a predetermined reference voltage. A selection circuit receives a selection signal and selects one of the divisional voltages. The selection circuit includes a plurality of first switch circuits selectively activated in response to the selection signal to select one of the divisional voltages. Each of the first switch circuits is provided with a logic switch function and has an ON resistance when activated. An activated one of the first switch circuits generates the pixel voltage by further dividing the selected one of the divisional voltages.

公开(公告)号：US20070296679A1

公开(公告)日：2007-12-27

申请号：US11890585

申请日：2007-08-06

申请人： Hideto Fukuda ,  Shinya Udo ,  Masao Kumagai ,  Osamu Kudo

发明人： Hideto Fukuda ,  Shinya Udo ,  Masao Kumagai ,  Osamu Kudo

IPC分类号： G09G3/36

CPC分类号： G09G3/2011 ,  G09G3/20 ,  G09G3/3614 ,  G09G3/3688 ,  G09G3/3696 ,  G09G2310/027 ,  G09G2310/0297 ,  H03M1/069 ,  H03M1/687 ,  H03M1/76 ,  H03M1/765

摘要： A drive circuit of a display that decreases the number of gates in a selection circuit to reduce chip area. The drive circuit includes a first voltage dividing circuit for generating a plurality of divisional voltages by dividing a predetermined reference voltage. A selection circuit receives a selection signal and selects one of the divisional voltages. The selection circuit includes a plurality of first switch circuits selectively activated in response to the selection signal to select one of the divisional voltages. Each of the first switch circuits is provided with a logic switch function and has an ON resistance when activated. An activated one of the first switch circuits generates the pixel voltage by further dividing the selected one of the divisional voltages.

公开(公告)号：US07903071B2

公开(公告)日：2011-03-08

申请号：US11890585

申请日：2007-08-06

申请人： Hideto Fukuda ,  Shinya Udo ,  Masao Kumagai ,  Osamu Kudo

发明人： Hideto Fukuda ,  Shinya Udo ,  Masao Kumagai ,  Osamu Kudo

IPC分类号： G09G3/36

CPC分类号： G09G3/2011 ,  G09G3/20 ,  G09G3/3614 ,  G09G3/3688 ,  G09G3/3696 ,  G09G2310/027 ,  G09G2310/0297 ,  H03M1/069 ,  H03M1/687 ,  H03M1/76 ,  H03M1/765

摘要： A driver IC for a display that includes a first D/A converter with a 1st selection circuit that receives 1st image signals and supplies a selected positive divisional voltage to a 1st operational amplifier, which supplies a positive pixel voltage by amplifying the selected positive divisional voltage; a 2nd D/A converter with a 2nd selection circuit that receives 2nd image signals and supplies a selected negative divisional voltage to a 2nd operational amplifier, which supplies a negative pixel voltage by amplifying the selected negative divisional voltage; and a polarity switching switch with 1st and 2nd switches connecting the 1st and 2nd D/A converters respectively, the polarity switching switch being switched to supply each of output terminals corresponding to the 1st and 2nd image signals alternately with the positive and negative pixel voltages every horizontal scan period by activating/inactivating the 1st and 2nd switches in a complementary manner.

摘要翻译： 一种用于显示器的驱动器IC，其包括具有第一选择电路的第一D / A转换器，所述第一选择电路接收第一图像信号并将选择的正分压提供给第一运算放大器，所述第一运算放大器通过放大所选择的正分压 ; 具有第二选择电路的第二D / A转换器，其接收第二图像信号并将选择的负分压提供给第二运算放大器，所述第二运算放大器通过放大所选择的负分压来提供负像素电压; 以及极性切换开关，具有分别连接第一和第二D / A转换器的第一和第二开关，极性切换开关被切换以与正，负像素电压交替地提供与第一和第二图像信号相对应的每个输出端子 水平扫描周期通过以互补的方式激活/停用第1和第2开关。

公开(公告)号：US06747624B1

公开(公告)日：2004-06-08

申请号：US09501009

申请日：2000-02-09

申请人： Shinya Udo ,  Osamu Kudo

发明人： Shinya Udo ,  Osamu Kudo

IPC分类号： G09G336

CPC分类号： G09G3/3685 ,  G09G3/3614 ,  G09G2310/027 ,  G09G2310/0297 ,  G09G2320/0233

摘要： In the LCD panel driving circuit, the voltage of first and second buffer amplifiers is supplied to first output pad, the voltage of second and third buffer amplifiers is supplied to second output pad, and voltage of third and fourth buffer amplifiers is supplied to third output pad. Thus, data-line selection switches and output-polarity selection switches are switched in such a way that the voltage supplied to any adjacent output pads is always supplied from adjacent buffer amplifiers.

摘要翻译： 在LCD面板驱动电路中，第一和第二缓冲放大器的电压被提供给第一输出焊盘，第二和第三缓冲放大器的电压被提供给第二输出焊盘，第三和第四缓冲放大器的电压被提供给第三输出 垫。 因此，数据线选择开关和输出极性选择开关被切换，使得提供给任何相邻输出焊盘的电压总是从相邻的缓冲放大器提供。

公开(公告)号：US07978168B2

公开(公告)日：2011-07-12

申请号：US11890437

申请日：2007-08-06

申请人： Hideto Fukuda ,  Shinya Udo ,  Masao Kumagai ,  Osamu Kudo

发明人： Hideto Fukuda ,  Shinya Udo ,  Masao Kumagai ,  Osamu Kudo

IPC分类号： G09G3/36

CPC分类号： G09G3/2011 ,  G09G3/20 ,  G09G3/3614 ,  G09G3/3688 ,  G09G3/3696 ,  G09G2310/027 ,  G09G2310/0297 ,  H03M1/069 ,  H03M1/687 ,  H03M1/76 ,  H03M1/765

摘要： A D/A converter for receiving a plurality of divisional voltages and converting a digital signal to an analog voltage with the divisional voltages, the D/A converter includes a selection circuit for receiving the divisional voltages and the digital signal to select one of the divisional voltages. The selection circuit includes a plurality of first switch circuits that are selectively activated in response to the digital signal to select one of the divisional voltages, with each of the first switch circuits being provided with a logic switch function and having an ON resistance when activated, and at least an activated one of the first switch circuits further dividing the selected one of the divisional voltages with the ON resistance. The plurality of switch circuits includes at least one voltage dividing switch circuit used to further divide the selected one of the divisional voltages.

摘要翻译： AD / A转换器，用于接收多个分压，并将数字信号转换为具有分压的模拟电压，D / A转换器包括用于接收分压的选择电路和数字信号，以选择分压之一 。 选择电路包括多个第一开关电路，其响应于数字信号选择性地激活以选择分压之一，其中每个第一开关电路被提供逻辑开关功能并且在被激活时具有导通电阻， 并且所述第一开关电路中的至少一个被激活的开关电路进一步用所述导通电阻将所选择的所述一个电压分压。 多个开关电路包括至少一个分压开关电路，用于进一步分割所选择的一个分压。

公开(公告)号：US20070296678A1

公开(公告)日：2007-12-27

申请号：US11890437

申请日：2007-08-06

申请人： Hideto Fukuda ,  Shinya Udo ,  Masao Kumagai ,  Osamu Kudo

发明人： Hideto Fukuda ,  Shinya Udo ,  Masao Kumagai ,  Osamu Kudo

IPC分类号： G09G3/36

CPC分类号： G09G3/2011 ,  G09G3/20 ,  G09G3/3614 ,  G09G3/3688 ,  G09G3/3696 ,  G09G2310/027 ,  G09G2310/0297 ,  H03M1/069 ,  H03M1/687 ,  H03M1/76 ,  H03M1/765

摘要： A drive circuit of a display that decreases the number of gates in a selection circuit to reduce chip area. The drive circuit includes a first voltage dividing circuit for generating a plurality of divisional voltages by dividing a predetermined reference voltage. A selection circuit receives a selection signal and selects one of the divisional voltages. The selection circuit includes a plurality of first switch circuits selectively activated in response to the selection signal to select one of the divisional voltages. Each of the first switch circuits is provided with a logic switch function and has an ON resistance when activated. An activated one of the first switch circuits generates the pixel voltage by further dividing the selected one of the divisional voltages.

摘要翻译： 一种显示器的驱动电路，其减少选择电路中的栅极数量以减少芯片面积。 驱动电路包括用于通过划分预定参考电压来产生多个分压的第一分压电路。 选择电路接收选择信号并选择分压之一。 选择电路包括响应于选择信号选择性地激活以选择分压之一的多个第一开关电路。 每个第一开关电路具有逻辑开关功能，并且在被激活时具有导通电阻。 第一开关电路中的被激活的一个通过进一步分割所选择的一个分压来产生像素电压。

公开(公告)号：US06864869B2

公开(公告)日：2005-03-08

申请号：US09732700

申请日：2000-12-11

申请人： Shinya Udo ,  Osamu Kudo

发明人： Shinya Udo ,  Osamu Kudo

IPC分类号： G02F1/133 ,  G09G3/00 ,  G09G3/20 ,  G09G3/36

CPC分类号： G09G3/2011 ,  G09G3/006 ,  G09G3/3688 ,  G09G2330/12

摘要： The present invention provides a data driver on which an operation test can be easily and reliably conducted at the stage of manufacture and for which the testing time can be reduced and a display utilizing the same. A select switch portion 60 is provided for electrically connecting and disconnecting a ladder resistor portion 56 and selector portions 58. At the ends of wiring of grayscale voltage lines l1 through l64 opposite to the ladder resistor portion 56, there is provided a state setting circuit 62 which sets each of the grayscale lines l1 through l64 at a “High” level or a “Low” level or which sets the ends of the grayscale voltage lines l1 through l64 in a high impedance state. The state setting circuit 62 is further connected to a testing control portion 64 incorporating a shift register which operates in synchronism with a test clock TST-CLK.

摘要翻译： 本发明提供一种数据驱动器，在制造阶段可以容易且可靠地进行操作测试，并且可以减少测试时间和使用它的显示器。 设置选择开关部60，用于电梯连接和断开梯形电阻部分56和选择部分58.在与梯形电阻部分56相对的灰度级电压线l1至l64的布线端部，设有状态设置电路62 其将灰度线l1至116中的每一个设置为“高”电平或“低”电平，或将灰度电压线l1至164的末端设置为高阻抗状态。 状态设置电路62进一步连接到结合有与测试时钟TST-CLK同步工作的移位寄存器的测试控制部分64。

公开(公告)号：US06301956B1

公开(公告)日：2001-10-16

申请号：US09458980

申请日：1999-12-10

申请人： Hideto Fujita ,  Osamu Kudo ,  Yoshiyuki Fujita ,  Toyokazu Maeda

发明人： Hideto Fujita ,  Osamu Kudo ,  Yoshiyuki Fujita ,  Toyokazu Maeda

IPC分类号： G01N342

CPC分类号： G01N3/42 ,  G01N2203/0647

摘要： A hardness tester for a large test material is downsized by shortening a stroke length of the x-y stage. A hardness tester in accordance with the invention transfers the laser irradiating unit 70 two-dimensionally along the X or Y axis and irradiate a laser beam on the material W under test placed on the stage 10. The tester also monitors the laser beam visually and determine a target position to be measured and transfers the monitoring unit 45 to the determined target position along the X or Y axis and monitor the position by means of the monitoring unit 45. If the position does not fall on a boundary between crystals, the loading unit 55 is two-dimensionally transferred and forms a dent on the position by means of the penetrator 55a. An image of the dent is captured by the monitoring unit 45 and the hardness is determined by calculating a diagonal length of the dent by image processing.

摘要翻译： 通过缩短x-y阶段的行程长度来缩小大型测试材料的硬度计。 根据本发明的硬度计根据X或Y轴二维地传送激光照射单元70，并将激光束照射在放置在载物台10上的试验材料W上。测试仪还可目测地监测激光束，并确定 要测量的目标位置，并且将监测单元45沿着X或Y轴传送到所确定的目标位置，并通过监视单元45监视位置。如果位置不落在晶体之间的边界上，则装载单元 55被二维转印，并通过穿透器55a在位置上形成凹痕。 通过监视单元45捕获凹痕的图像，并且通过图像处理计算凹痕的对角线长度来确定硬度。

公开(公告)号：US4358752A

公开(公告)日：1982-11-09

申请号：US208385

申请日：1980-11-19

申请人： Haruo Tamada ,  Osamu Kudo

发明人： Haruo Tamada ,  Osamu Kudo

IPC分类号： G01R19/165 ,  G01R19/25 ,  G01R19/257 ,  H03F3/34 ,  H03K5/08 ,  H03K5/24 ,  H03M1/00 ,  H03M1/34 ,  H03M1/38 ,  H03K13/02

CPC分类号： H03K5/2418 ,  H03M1/40 ,  H03M1/46 ,  H03M1/74

摘要： A differential amplifier, which is associated with a digital-to-analog converter and a register and serves as an element of an analog-to-digital converter, having the offset input voltage characteristic determined by selecting, for example, the ratio of the emitter areas of a first pair of transistors so that no offset characteristic is required for the digital-to-analog converter associated with the differential amplifier. The offset input voltage can also be determined by selecting the ratio of the emitter areas of a second pair of transistors each one of the second pair of transistors connected to a different one of the first transistors and each one of the second pair of transistors having a current source of the same magnitude. The offset characteristic can also be determined by selecting unequal magnitudes of the current sources connected to the second pair of transistors when the ratio of the second pair of transistor emitter areas are equal. The offset characteristic can also be selected by selecting both the second pair of transistors emitter areas ratios and the second transistor current source magnitudes as not equal or by selecting any combination of the above current magnitudes or emitter area ratios.

摘要翻译： 差分放大器，其与数模转换器和寄存器相关联，并且用作模数转换器的元件，其具有通过选择例如发射极的比例确定的偏移输入电压特性 第一对晶体管的区域，使得与差分放大器相关联的数模转换器不需要偏移特性。 偏移输入电压也可以通过选择第二对晶体管中的每一个晶体管的发射极面积与第一晶体管中的不同一个晶体管连接的第二对晶体管的发射极面积的比例来确定，并且第二对晶体管中的每一个晶体管具有 电流源的幅度相同。 当第二对晶体管发射极区域的比率相等时，也可以通过选择连接到第二对晶体管的电流源的不等量来确定偏移特性。 还可以通过选择第二对晶体管发射极面积比和第二晶体管电流源幅度不相等或通过选择上述电流幅度或发射极面积比的任何组合来选择偏移特性。