公开(公告)号：US07205201B2

公开(公告)日：2007-04-17

申请号：US10914943

申请日：2004-08-09

Applicant: Chih-Feng Huang ,  Ta-yung Yang ,  Jenn-yu G. Lin ,  Tuo-Hsin Chien

Inventor： Chih-Feng Huang ,  Ta-yung Yang ,  Jenn-yu G. Lin ,  Tuo-Hsin Chien

IPC: H01L21/8234

CPC classification number: H01L21/823814 ,  H01L21/823857 ,  H01L21/823892

Abstract: A method of manufacturing different-voltage devices mainly comprises forming at least one high-voltage well in high-voltage device regions, at least one N-well in low-voltage device regions, at least one P-well in low-voltage device regions, source/drain wells in high-voltage device regions, and isolation wells in isolation regions in a p-type substrate. The breakdown voltage is adjusted by modulating the ion doping profile. Furthermore, parameters of implanting conductive ions are adjusted for implanting conductive ions into both high-voltage device regions and low-voltage device regions. The isolation wells formed in isolation regions between devices are for separating device formed over high-voltage device regions and device formed over low-voltage device regions. The thickness of a HV gate oxide layer is thicker than the thickness of an LV gate oxide layer for modulating threshold voltages of high-voltage devices and low-voltage devices.

Abstract translation: 一种制造不同电压装置的方法主要包括在高电压装置区域中形成至少一个高电压阱，在低电压装置区域中形成至少一个N阱，在低电压装置区域中形成至少一个P阱 ，高压器件区域中的源/漏极阱以及p型衬底中的隔离区中的隔离阱。 通过调制离子掺杂分布来调整击穿电压。 此外，调整注入导电离子的参数，以将导电离子注入到高电压器件区域和低电压器件区域中。 在器件之间的隔离区域中形成的隔离阱用于在高电压器件区域上形成的分离器件和在低电压器件区域上形成的器件。 HV栅极氧化物层的厚度比用于调制高电压器件和低电压器件的阈值电压的LV栅极氧化物层的厚度厚。

公开(公告)号：US20070001229A1

公开(公告)日：2007-01-04

申请号：US11174018

申请日：2005-07-01

Applicant: Chih-Feng Huang ,  Ta-yung Yang ,  Jenn-yu Lin ,  Tuo-Hsin Chien

Inventor： Chih-Feng Huang ,  Ta-yung Yang ,  Jenn-yu Lin ,  Tuo-Hsin Chien

IPC: H01L23/62

CPC classification number: H01L29/87

Abstract: An electrostatic discharge (ESD) device has a parasitic SCR structure and a controllable trigger voltage. The controllable trigger voltage of the ESD device is achieved by modulating a distance between an edge of a lightly doped well and an edge of a heavily doped region located at two ends of the lightly doped well. Since the distance and the trigger voltage are linearly proportional, the trigger voltage can be set to a specific value from a minimum value to a maximum value.

Abstract translation: 静电放电（ESD）器件具有寄生SCR结构和可控触发电压。 通过调制轻掺杂阱的边缘和位于轻掺杂阱的两端的重掺杂区的边缘之间的距离来实现ESD器件的可控触发电压。 由于距离和触发电压是线性比例的，因此可以将触发电压设置为从最小值到最大值的特定值。

公开(公告)号：US20060030107A1

公开(公告)日：2006-02-09

申请号：US10914943

申请日：2004-08-09

Applicant: Chih-Feng Huang ,  Ta-yung Yang ,  Jenn-yu Lin ,  Tuo-Hsin Chien

Inventor： Chih-Feng Huang ,  Ta-yung Yang ,  Jenn-yu Lin ,  Tuo-Hsin Chien

IPC: H01L21/8234

CPC classification number: H01L21/823814 ,  H01L21/823857 ,  H01L21/823892

Abstract: A method of manufacturing different-voltage devices mainly comprises forming at least one high-voltage well in high-voltage device regions, at least one N-well in low-voltage device regions, at least one P-well in low-voltage device regions, source/drain wells in high-voltage device regions, and isolation wells in isolation regions in a p-type substrate. The breakdown voltage is adjusted by modulating the ion doping profile. Furthermore, parameters of implanting conductive ions are adjusted for implanting conductive ions into both high-voltage device regions and low-voltage device regions. The isolation wells formed in isolation regions between devices are for separating device formed over high-voltage device regions and device formed over low-voltage device regions. The thickness of a HV gate oxide layer is thicker than the thickness of an LV gate oxide layer for modulating threshold voltages of high-voltage devices and low-voltage devices.

Abstract translation: 一种制造不同电压装置的方法主要包括在高电压装置区域中形成至少一个高电压阱，在低电压装置区域中形成至少一个N阱，在低电压装置区域中形成至少一个P阱 ，高压器件区域中的源/漏极阱以及p型衬底中的隔离区中的隔离阱。 通过调制离子掺杂分布来调整击穿电压。 此外，调整注入导电离子的参数，以将导电离子注入到高电压器件区域和低电压器件区域中。 在器件之间的隔离区域中形成的隔离阱用于在高电压器件区域上形成的分离器件和在低电压器件区域上形成的器件。 HV栅极氧化物层的厚度比用于调制高电压器件和低电压器件的阈值电压的LV栅极氧化物层的厚度厚。

公开(公告)号：US06995428B2

公开(公告)日：2006-02-07

申请号：US10786703

申请日：2004-02-24

Applicant: Chih-Feng Huang ,  Ta-yung Yang ,  Jenn-yu G. Lin ,  Tuo-Hsin Chien

Inventor： Chih-Feng Huang ,  Ta-yung Yang ,  Jenn-yu G. Lin ,  Tuo-Hsin Chien

IPC: H01L29/76

CPC classification number: H01L29/0634 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/42368 ,  H01L29/7816

Abstract: A high voltage LDMOS transistor according to the present invention includes a P-field and divided P-fields in an extended drain region of a N-well. The P-field and divided P-fields form junction-fields in the N-well, in which a drift region is fully depleted before breakdown occurs. Therefore, a higher breakdown voltage is achieved and a higher doping density of the N-well is allowed. Higher doping density can effectively reduce the on-resistance of the LDMOS transistor. Furthermore, the N-well generated beneath a source diffusion region provides a low-impedance path for a source region, which restrict the transistor current flow in between a drain region and a source region.

Abstract translation: 根据本发明的高电压LDMOS晶体管包括在N阱的扩展漏极区域中的P场和分割的P场。 P场和分割的P场在N阱中形成结场，其中漂移区在击穿之前被完全耗尽。 因此，实现更高的击穿电压，并且允许N阱的较高的掺杂密度。 较高的掺杂密度可以有效降低LDMOS晶体管的导通电阻。 此外，在源极扩散区域之下产生的N阱为源极区域提供了低阻抗路径，其限制了漏极区域和源极区域之间的晶体管电流。

公开(公告)号：US20050184338A1

公开(公告)日：2005-08-25

申请号：US10786703

申请日：2004-02-24

Applicant: Chih-Feng Huang ,  Ta-Yung Yang ,  Jenn-Yu Lin ,  Tuo-Hsin Chien

Inventor： Chih-Feng Huang ,  Ta-Yung Yang ,  Jenn-Yu Lin ,  Tuo-Hsin Chien

IPC: H01L21/336 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/735 ,  H01L29/739 ,  H01L29/772 ,  H01L29/78 ,  H01L29/94

CPC classification number: H01L29/0634 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/42368 ,  H01L29/7816

Abstract: A high voltage LDMOS transistor according to the present invention includes a P-field and divided P-fields in an extended drain region of a N-well. The P-field and divided P-fields form junction-fields in the N-well, in which a drift region is fully depleted before breakdown occurs. Therefore, a higher breakdown voltage is achieved and a higher doping density of the N-well is allowed. Higher doping density can effectively reduce the on-resistance of the LDMOS transistor. Furthermore, the N-well generated beneath a source diffusion region provides a low-impedance path for a source region, which restrict the transistor current flow in between a drain region and a source region.

Abstract translation: 根据本发明的高电压LDMOS晶体管包括在N阱的扩展漏极区域中的P场和分割的P场。 P场和分割的P场在N阱中形成结场，其中漂移区在击穿之前被完全耗尽。 因此，实现更高的击穿电压，并且允许N阱的较高的掺杂密度。 较高的掺杂密度可以有效降低LDMOS晶体管的导通电阻。 此外，在源极扩散区域之下产生的N阱为源极区域提供了低阻抗路径，其限制了漏极区域和源极区域之间的晶体管电流。

公开(公告)号：US06873011B1

公开(公告)日：2005-03-29

申请号：US10786701

申请日：2004-02-24

Applicant: Chih-Feng Huang ,  Ta-yung Yang ,  Jenn-yu G. Lin ,  Tuo-Hsin Chien

Inventor： Chih-Feng Huang ,  Ta-yung Yang ,  Jenn-yu G. Lin ,  Tuo-Hsin Chien

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/94

CPC classification number: H01L29/7816 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0696

Abstract: A high voltage LDMOS transistor according to the present invention includes P-field blocks in the extended drain region of a N-well. The P-field blocks form the junction-fields in the N-well for equalizing the capacitance of parasitic capacitors between the drain region and the source region and fully deplete the drift region before breakdown occurs. A higher breakdown voltage is therefore achieved and the N-well having a higher doping density is thus allowed. The higher doping density reduces the on-resistance of the transistor. Furthermore, the portion of the N-well generated beneath the source diffusion region produces a low-impedance path for the source region, which restricts the transistor current flow in between the drain region and the source region.

Abstract translation: 根据本发明的高电压LDMOS晶体管包括N阱扩展漏极区中的P场区块。 P-场块形成N阱中的结场，用于均衡漏极区域和源极区域之间的寄生电容器的电容，并且在击穿之前完全耗尽漂移区域。 因此实现更高的击穿电压，因此允许具有较高掺杂密度的N阱。 较高的掺杂密度降低了晶体管的导通电阻。 此外，在源极扩散区域之下产生的N阱的部分产生用于源极区域的低阻抗路径，其限制了漏极区域和源极区域之间的晶体管电流。

公开(公告)号：US07847365B2

公开(公告)日：2010-12-07

申请号：US11913037

申请日：2005-10-14

Applicant: Chih-Feng Huang ,  Tuo-Hsin Chien ,  Jenn-Yu Lin ,  Ta-yung Yang

Inventor： Chih-Feng Huang ,  Tuo-Hsin Chien ,  Jenn-Yu Lin ,  Ta-yung Yang

IPC: H01L29/78

CPC classification number: H01L27/0928 ,  H01L21/823878 ,  H01L21/823892

Abstract: A MOSFET device with an isolation structure for a monolithic integration is provided. A P-type MOSFET includes a first N-well disposed in a P-type substrate, a first P-type region disposed in the first N-well, a P+ drain region disposed in the first P-type region, a first source electrode formed with a P+ source region and an N+ contact region. The first N-well surrounds the P+ source region and the N+ contact region. An N-type MOSFET includes a second N-well disposed in a P-type substrate, a second P-type region disposed in the second N-well, an N+drain region disposed in the second N-well, a second source electrode formed with an N+ source region and a P+ contact region. The second P-type region surrounds the N+ source region and the P+ contact region. A plurality of separated P-type regions is disposed in the P-type substrate to provide isolation for transistors.

Abstract translation: 提供了具有用于单片集成的隔离结构的MOSFET器件。 P型MOSFET包括设置在P型衬底中的第一N阱，设置在第一N阱中的第一P型区，设置在第一P型区中的P +漏极区，第一源电极 形成有P +源极区域和N +接触区域。 第一个N阱围绕着P +源极区域和N +接触区域。 N型MOSFET包括设置在P型衬底中的第二N阱，设置在第二N阱中的第二P型区，设置在第二N阱中的N +漏极区，第二源电极 形成有N +源区和P +接触区。 第二P型区围绕N +源区和P +接触区。 多个分离的P型区域设置在P型衬底中以提供晶体管的隔离。

公开(公告)号：US07417287B2

公开(公告)日：2008-08-26

申请号：US11174018

申请日：2005-07-01

Applicant: Chih-Feng Huang ,  Ta-yung Yang ,  Jenn-yu G. Lin ,  Tuo-Hsin Chien

Inventor： Chih-Feng Huang ,  Ta-yung Yang ,  Jenn-yu G. Lin ,  Tuo-Hsin Chien

IPC: H01L27/01 ,  H01L31/0392

CPC classification number: H01L29/87

Abstract: An electrostatic discharge (ESD) device has a parasitic SCR structure and a controllable trigger voltage. The controllable trigger voltage of the ESD device is achieved by modulating a distance between an edge of a lightly doped well and an edge of a heavily doped region located at two ends of the lightly doped well. Since the distance and the trigger voltage are linearly proportional, the trigger voltage can be set to a specific value from a minimum value to a maximum value.

Abstract translation: 静电放电（ESD）器件具有寄生SCR结构和可控触发电压。 通过调制轻掺杂阱的边缘和位于轻掺杂阱的两端的重掺杂区的边缘之间的距离来实现ESD器件的可控触发电压。 由于距离和触发电压是线性比例的，因此可以将触发电压设置为从最小值到最大值的特定值。

公开(公告)号：US20070178648A1

公开(公告)日：2007-08-02

申请号：US11682621

申请日：2007-03-06

Applicant: Chih-Feng Huang ,  Ta-yung Yang ,  Jenn-yu Lin ,  Tuo-Hsin Chien

Inventor： Chih-Feng Huang ,  Ta-yung Yang ,  Jenn-yu Lin ,  Tuo-Hsin Chien

IPC: H01L21/8234

CPC classification number: H01L21/823814 ,  H01L21/823857 ,  H01L21/823892

Abstract: A method of manufacturing different-voltage devices mainly comprises forming at least one high-voltage well in high-voltage device regions, at least one N-well in low-voltage device regions, at least one P-well in low-voltage device regions, source/drain wells in high-voltage device regions, and isolation wells in isolation regions in a p-type substrate. The breakdown voltage is adjusted by modulating the ion doping profile. Furthermore, parameters of implanting conductive ions are adjusted for implanting conductive ions into both high-voltage device regions and low-voltage device regions. The isolation wells formed in isolation regions between devices are for separating device formed over high-voltage device regions and device formed over low-voltage device regions. The thickness of a HV gate oxide layer is thicker than the thickness of an LV gate oxide layer for modulating threshold voltages of high-voltage devices and low-voltage devices.

Abstract translation: 一种制造不同电压装置的方法主要包括在高电压装置区域中形成至少一个高电压阱，在低电压装置区域中形成至少一个N阱，在低电压装置区域中形成至少一个P阱 ，高压器件区域中的源/漏极阱以及p型衬底中的隔离区中的隔离阱。 通过调制离子掺杂分布来调整击穿电压。 此外，调整注入导电离子的参数，以将导电离子注入到高电压器件区域和低电压器件区域中。 在器件之间的隔离区域中形成的隔离阱用于在高电压器件区域上形成的分离器件和在低电压器件区域上形成的器件。 HV栅极氧化物层的厚度比用于调制高电压器件和低电压器件的阈值电压的LV栅极氧化物层的厚度厚。

公开(公告)号：US20070052032A1

公开(公告)日：2007-03-08

申请号：US11223745

申请日：2005-09-08

Applicant: Chih-Feng Huang ,  Ta-yung Yang ,  Jenn-yu Lin ,  Tuo-Hsin Chien

Inventor： Chih-Feng Huang ,  Ta-yung Yang ,  Jenn-yu Lin ,  Tuo-Hsin Chien

IPC: H01L23/62

CPC classification number: H01L27/0262 ,  H01L27/0921

Abstract: An electrostatic discharge (ESD) device with latch-up immunity is provided. The ESD device has an equivalent SCR structure when a supply voltage is not applied thereto and has an equivalent PN diode structure when the supply voltage is applied thereto, thus freeing the ESD device from the latch-up phenomenon.

Abstract translation: 提供具有闭锁抑制的静电放电（ESD）器件。 当不施加电源电压时，ESD器件具有等效的SCR结构，并且当施加电源电压时具有等效的PN二极管结构，从而使ESD器件免于闩锁现象。