Fast turn on silicon controlled rectifiers for ESD protection
    11.
    发明授权
    Fast turn on silicon controlled rectifiers for ESD protection 有权
    快速开启可控硅整流器,实现ESD保护

    公开(公告)号:US08692289B2

    公开(公告)日:2014-04-08

    申请号:US13558154

    申请日:2012-07-25

    CPC classification number: H01L27/0817 H01L27/0262 H01L29/7436

    Abstract: Fast turn on silicon controlled rectifiers for ESD protection. A semiconductor device includes a semiconductor substrate of a first conductivity type; a first well of a second conductivity type; a second well of the second conductivity type; a first diffused region of the first conductivity type and coupled to a first terminal; a first diffused region of the second conductivity type; a second diffused region of the first conductivity type; a second diffused region of the second conductivity type in the second well; wherein the first diffused region of the first conductivity type and the first diffused region of the second conductivity type form a first diode, and the second diffused region of the first conductivity type and the second diffused region of the second conductivity type form a second diode, and the first and second diodes are series coupled between the first terminal and the second terminal.

    Abstract translation: 快速开启可控硅整流器,实现ESD保护。 半导体器件包括第一导电类型的半导体衬底; 第二导电类型的第一阱; 第二导电类型的第二阱; 第一导电类型的第一扩散区域并耦合到第一端子; 第二导电类型的第一扩散区域; 第一导电类型的第二扩散区域; 第二导电类型的第二扩散区域; 其中第一导电类型的第一扩散区域和第二导电类型的第一扩散区域形成第一二极管,并且第一导电类型的第二扩散区域和第二导电类型的第二扩散区域形成第二二极管, 并且第一和第二二极管串联耦合在第一端子和第二端子之间。

    Method for Forming Silicon Thin Film
    12.
    发明申请
    Method for Forming Silicon Thin Film 审中-公开
    形成硅薄膜的方法

    公开(公告)号:US20120329203A1

    公开(公告)日:2012-12-27

    申请号:US13166352

    申请日:2011-06-22

    Abstract: The present invention is to provide a method of creating a PIN silicon thin film comprising the steps of providing a molten P-type, Intrinsic and N-type semiconductor material. Next, it is performing a down draw process or a casting process of the molten P-type. Intrinsic and N-type semiconductor material. Then, it is selectively performing a dual-side rolling process to create a P-type, Intrinsic and N-type semiconductor ribbon. Subsequently, it is performing a step of joining the P-type, Intrinsic and N-type semiconductor ribbon to form a PIN semiconductor ribbon. Finally, it is performing a roll press process or a pressing process to the PIN semiconductor ribbon to create the PIN semiconductor thin film.

    Abstract translation: 本发明提供一种制造PIN硅薄膜的方法,其包括提供熔融P型,本征型和N型半导体材料的步骤。 接下来,正在进行熔融P型的下拉工序或铸造工序。 本征和N型半导体材料。 然后,选择性地执行双面轧制工艺以产生P型,本征和N型半导体带。 随后,正在执行连接P型,本征和N型半导体带以形成PIN半导体带的步骤。 最后,对PIN半导体薄带进行辊压加工或压制加工以产生PIN半导体薄膜。

    ESD PROTECTION TECHNIQUES
    13.
    发明申请
    ESD PROTECTION TECHNIQUES 有权
    ESD保护技术

    公开(公告)号:US20130050885A1

    公开(公告)日:2013-02-28

    申请号:US13217533

    申请日:2011-08-25

    CPC classification number: H02H9/04 H02H9/046

    Abstract: Some embodiments relate to an electrostatic discharge (ESD) protection device to protect a circuit that is electrically connected to first and second circuit nodes from an ESD event. The ESD protection device includes a first electrical path extending between the first and second circuit nodes and including first and second ESD detection elements arranged thereon. The ESD protection device also includes first and second voltage bias elements having respective inputs electrically connected to respective outputs of the first and second ESD detection elements. A second electrical path extends between the first and second circuit nodes and is in parallel with the first electrical path. The second electrical path includes a voltage controlled shunt network having at least two control terminals electrically connected to respective outputs of the first and second voltage bias elements. Other embodiments are also disclosed.

    Abstract translation: 一些实施例涉及用于保护电连接到第一和第二电路节点的电路与ESD事件的静电放电(ESD)保护装置。 ESD保护装置包括在第一和第二电路节点之间延伸并且包括布置在其上的第一和第二ESD检测元件的第一电路径。 ESD保护装置还包括具有电连接到第一和第二ESD检测元件的相应输出的相应输入的第一和第二电压偏置元件。 第二电路在第一和第二电路节点之间延伸并与第一电路平行。 第二电路包括电压控制并联网络,其具有电连接到第一和第二电压偏置元件的相应输出的至少两个控制端子。 还公开了其他实施例。

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