公开(公告)号：US06222476B1

公开(公告)日：2001-04-24

申请号：US09386029

申请日：1999-08-30

Applicant: Sang-Soo Lee ,  Tzu-Wang Pan

Inventor： Sang-Soo Lee ,  Tzu-Wang Pan

IPC: H03M136

CPC classification number: H03M1/0863 ,  H03M1/365

Abstract: A system and method for reduced metastability errors in an analog-to-digital converter (“ADC”) are disclosed. The ADC comprises comparators configured to output a thermometer code and a thermometer-to-binary encoder for converting the thermometer code to a digital output. The thermometer-to-binary encoder includes a transition detection logic to generate a transition codeword having at least one transition bit corresponding to a transition point in the thermometer code, an intermediate encoding logic to encode the transition codeword into first intermediate signals, a converter logic to convert the first intermediate signals into converted intermediate signals such that same converted intermediate signals result from first intermediate signals corresponding to a transition codeword having more than one transition bit and first intermediate signals corresponding to another transition codeword having one of the more than one transition bit, and a converted signals mapper for mapping the converted signals to the digital output. The transition detection logic may include inverters and AND gates where a threshold voltage of each inverter is preferably greater than a threshold voltage of each corresponding AND gate to which the output of each inverter is input.

Abstract translation: 公开了一种用于降低模拟 - 数字转换器（“ADC”）中的亚稳态误差的系统和方法。 ADC包括比较器，其配置为输出温度计代码和用于将温度计代码转换为数字输出的温度计与二进制编码器。 温度计对二进制编码器包括转换检测逻辑，以产生具有对应于温度计代码中的转变点的至少一个转换位的转换码字，将转换码字编码为第一中间信号的中间编码逻辑，转换器逻辑 将第一中间信号转换成转换的中间信号，使得相同的转换的中间信号由对应于具有多于一个转换位的转换码字的第一中间信号和对应于具有多于一个转换位之一的另一个转换码字的第一中间信号产生 ，以及用于将转换的信号映射到数字输出的转换信号映射器。 转换检测逻辑可以包括反相器和与门，其中每个反相器的阈值电压优选地大于每个反相器的输出输入到的每个对应的与门的阈值电压。

公开(公告)号：US5465059A

公开(公告)日：1995-11-07

申请号：US228758

申请日：1994-04-18

Applicant: Tzu-Wang Pan ,  Richard Yamasaki

Inventor： Tzu-Wang Pan ,  Richard Yamasaki

IPC: G11B5/09 ,  G11B20/14 ,  H03D13/00 ,  H03L7/091 ,  H04L7/02 ,  H04L7/033 ,  H04L7/04 ,  H04L7/10 ,  H04L25/497 ,  G01R29/00

CPC classification number: H04L7/0062 ,  G11B20/10055 ,  G11B20/1403 ,  G11B5/09 ,  H03D13/00 ,  H03L7/091 ,  H04L25/497 ,  H04L7/033 ,  H04L7/046 ,  H04L7/10

Abstract: A method and apparatus for timing acquisition of partial response class IV Signaling is described. The invention uses an acquisition logic block to determine an output sequence that best matches a preamble pattern. The logic block analyzes current quantizer output X and the two previous decisions X.sub.n and X.sub.n-1. The logic uses these values to determine the next value X.sub.n+1 so that the best match occurs. The invention is implemented with OR gates, AND gates, and D flip-flops and can operate in acquiring mode or tracking mode.

Abstract translation: 描述了用于部分响应等级IV信令的定时采集的方法和装置。 本发明使用采集逻辑块来确定与前同步码模式最佳匹配的输出序列。 逻辑块分析当前的量化器输出X和前面的两个决定Xn和Xn-1。 逻辑使用这些值来确定下一个值Xn + 1，以便发生最佳匹配。 本发明用OR门，AND门和D触发器实现，并且可以在获取模式或跟踪模式下操作。

公开(公告)号：US08472890B2

公开(公告)日：2013-06-25

申请号：US11947597

申请日：2007-11-29

Applicant: Wei Zhuo ,  Aristotele Hadjichristos ,  Tzu-wang Pan

Inventor： Wei Zhuo ,  Aristotele Hadjichristos ,  Tzu-wang Pan

IPC: H04B1/40

CPC classification number: H04B1/109 ,  H04B1/525

Abstract: A communication device includes a transmitter and a receiver. The receiver mixes a local oscillator (LO) signal with the received signal to downconvert the received signal to an intermediate frequency (IF). The LO path that feeds the LO signal to the downconverting mixer is controlled based on the transmit power of the transmitter. For high transmit power, the drive of the LO path is increased, thereby increasing the signal-to-noise ratio of the LO signal input into the mixer. For low transmit power levels, the drive to the LO path is decreased, reducing power consumption in the communication device. In this way, receiver path noise due to mixing of the LO phase noise with the self-generated transmitter signal is selectively controlled while incurring lower power consumption penalty. The communication device may be an access terminal configured for communication with a cellular radio network.

Abstract translation: 通信设备包括发射机和接收机。 接收器将本地振荡器（LO）信号与接收到的信号混合，以将接收到的信号下变频到中频（IF）。 基于发射机的发射功率来控制将LO信号馈送到下变频混频器的LO路径。 对于高发射功率，LO路径的驱动增加，从而增加输入混频器的LO信号的信噪比。 对于低发射功率电平，降低LO路径的驱动，从而降低通信设备的功耗。 以这种方式，由于LO相位噪声与自发送发射机信号的混合引起的接收机路径噪声被选择性地控制，同时产生较低的功耗损失。 通信设备可以是被配置为与蜂窝无线电网络进行通信的接入终端。

公开(公告)号：US20100330941A1

公开(公告)日：2010-12-30

申请号：US12492407

申请日：2009-06-26

Applicant: Pushp Trikha ,  Tzu-wang Pan ,  Eugene Yang ,  Yi Zeng ,  I-Hsiang Lin ,  Tg Vishwanath

Inventor： Pushp Trikha ,  Tzu-wang Pan ,  Eugene Yang ,  Yi Zeng ,  I-Hsiang Lin ,  Tg Vishwanath

IPC: H04B1/18

CPC classification number: H04H20/57 ,  H04H40/45

Abstract: A frequency modulation (FM) transmitter implemented with a delta-sigma modulator and a phase-locked loop (PLL) is described. The delta-sigma modulator receives a modulating signal (e.g., an FM stereo multiplex (MPX) signal) and provides a modulator output signal. The PLL performs frequency modulation based on the modulator output signal and provides an FM signal. The FM transmitter may further include a gain/phase compensation unit and a scaling unit. The compensation unit may compensate the modulating signal for the closed-loop response of the PLL. The scaling unit may scale the amplitude of the modulating signal based on a gain to obtain a target frequency deviation for the FM signal. The PLL may operate in a transmit mode or a receive mode, may perform frequency modulation in the transmit mode, and may provide a local oscillator (LO) signal at a fixed frequency in the receive mode.

Abstract translation: 描述了用Δ-Σ调制器和锁相环（PLL）实现的频率调制（FM）发射机。 Δ-Σ调制器接收调制信号（例如，FM立体声多路复用（MPX）信号），并提供调制器输出信号。 PLL根据调制器输出信号进行调频，并提供FM信号。 FM发射机还可以包括增益/相位补偿单元和缩放单元。 补偿单元可以补偿PLL的闭环响应的调制信号。 缩放单元可以基于增益来调整调制信号的幅度，以获得FM信号的目标频率偏差。 PLL可以以发送模式或接收模式工作，可以在发送模式下执行频率调制，并且可以在接收模式下以固定频率提供本地振荡器（LO）信号。

公开(公告)号：US20090130994A1

公开(公告)日：2009-05-21

申请号：US11947597

申请日：2007-11-29

Applicant: Wei Zhuo ,  Aristotele Hadjichristos ,  Tzu-wang Pan

Inventor： Wei Zhuo ,  Aristotele Hadjichristos ,  Tzu-wang Pan

IPC: H04B1/40 ,  H04B1/04

CPC classification number: H04B1/109 ,  H04B1/525

Abstract: A communication device includes a transmitter and a receiver. The receiver mixes a local oscillator (LO) signal with the received signal to downconvert the received signal to an intermediate frequency (IF). The LO path that feeds the LO signal to the downconverting mixer is controlled based on the transmit power of the transmitter. For high transmit power, the drive of the LO path is increased, thereby increasing the signal-to-noise ratio of the LO signal input into the mixer. For low transmit power levels, the drive to the LO path is decreased, reducing power consumption in the communication device. In this way, receiver path noise due to mixing of the LO phase noise with the self-generated transmitter signal is selectively controlled while incurring lower power consumption penalty. The communication device may be an access terminal configured for communication with a cellular radio network.

Abstract translation: 通信设备包括发射机和接收机。 接收器将本地振荡器（LO）信号与接收到的信号混合，以将接收到的信号下变频到中频（IF）。 基于发射机的发射功率来控制将LO信号馈送到下变频混频器的LO路径。 对于高发射功率，LO路径的驱动增加，从而增加输入混频器的LO信号的信噪比。 对于低发射功率电平，降低LO路径的驱动，从而降低通信设备的功耗。 以这种方式，由于LO相位噪声与自发送发射机信号的混合引起的接收机路径噪声被选择性地控制，同时产生较低的功耗损失。 通信设备可以是被配置为与蜂窝无线电网络进行通信的接入终端。

公开(公告)号：US06563889B1

公开(公告)日：2003-05-13

申请号：US09165182

申请日：1998-10-01

Applicant: Shih-Ming Shih ,  Tzu-wang Pan ,  Richard A. Contreras

Inventor： Shih-Ming Shih ,  Tzu-wang Pan ,  Richard A. Contreras

IPC: G11B500

CPC classification number: G11B20/10009 ,  G11B20/18

Abstract: A system and method are disclosed for equalizing a read signal from a data storage media is disclosed. An analog output signal is equalized by reading the data storage media using an analog equalization filter. The analog output of the analog equalization filter is converted to a raw digital output signal. The raw digital output signal is processed to detect and correct an error in the raw digital output signal. The error is detected and an adjustment is made to the boost of the analog equalization filter according to the error detected.

Abstract translation: 公开了一种用于均衡来自数据存储介质的读取信号的系统和方法。 通过使用模拟均衡滤波器读取数据存储介质来使模拟输出信号相等。 模拟均衡滤波器的模拟输出转换为原始数字输出信号。 处理原始数字输出信号以检测和纠正原始数字输出信号中的错误。 检测到错误，根据检测到的错误对模拟均衡滤波器的升压进行调整。

公开(公告)号：US08688045B2

公开(公告)日：2014-04-01

申请号：US12274167

申请日：2008-11-19

Applicant: I-Hsiang Lin ,  Tzu-wang Pan ,  Yi Zeng

Inventor： I-Hsiang Lin ,  Tzu-wang Pan ,  Yi Zeng

IPC: H04B1/00

CPC classification number: H04B1/525

Abstract: Exemplary embodiments include a frequency modulation (FM) transmitter and a non-FM receiver, which may be implemented on the same IC chip. The FM transmitter may include a digital FM modulator, a lowpass filter, an amplifier, and an LC tank circuit. The digital FM modulator may receive a digital input signal, perform FM modulation with the digital input signal, and provide a digital FM signal. The lowpass filter may filter the digital FM signal and provide a filtered FM signal. The amplifier may amplify the filtered FM signal and provide an output FM signal. The LC tank circuit may filter the output FM signal. The digital FM modulator may perform FM modulation by changing a variable divider ratio of a multi-modulus divider within a PLL. A delta-sigma modulator may receive the digital input signal and generate a modulator output signal used to obtain the variable divider ratio.

Abstract translation: 示例性实施例包括可以在同一IC芯片上实现的调频（FM）发射机和非FM接收机。 FM发射机可以包括数字FM调制器，低通滤波器，放大器和LC电路。 数字FM调制器可以接收数字输入信号，使用数字输入信号执行FM调制，并提供数字FM信号。 低通滤波器可以对数字FM信号进行滤波并提供滤波后的FM信号。 放大器可以放大经滤波的FM信号并提供输出FM信号。 LC振荡电路可以对输出的FM信号进行滤波。 数字FM调制器可以通过改变PLL内的多模式分频器的可变分频比来执行FM调制。 Δ-Σ调制器可以接收数字输入信号并产生用于获得可变分频比的调制器输出信号。

公开(公告)号：US08442466B2

公开(公告)日：2013-05-14

申请号：US12492407

申请日：2009-06-26

Applicant: Pushp Trikha ,  Tzu-wang Pan ,  Eugene Yang ,  Yi Zeng ,  I-Hsiang Lin ,  Tg Vishwanath

Inventor： Pushp Trikha ,  Tzu-wang Pan ,  Eugene Yang ,  Yi Zeng ,  I-Hsiang Lin ,  Tg Vishwanath

IPC: H04B1/06 ,  H04B7/00

CPC classification number: H04H20/57 ,  H04H40/45

Abstract: A frequency modulation (FM) transmitter implemented with a delta-sigma modulator and a phase-locked loop (PLL) is described. The delta-sigma modulator receives a modulating signal (e.g., an FM stereo multiplex (MPX) signal) and provides a modulator output signal. The PLL performs frequency modulation based on the modulator output signal and provides an FM signal. The FM transmitter may further include a gain/phase compensation unit and a scaling unit. The compensation unit may compensate the modulating signal for the closed-loop response of the PLL. The scaling unit may scale the amplitude of the modulating signal based on a gain to obtain a target frequency deviation for the FM signal. The PLL may operate in a transmit mode or a receive mode, may perform frequency modulation in the transmit mode, and may provide a local oscillator (LO) signal at a fixed frequency in the receive mode.

Abstract translation: 描述了用Δ-Σ调制器和锁相环（PLL）实现的频率调制（FM）发射机。 Δ-Σ调制器接收调制信号（例如，FM立体声多路复用（MPX）信号），并提供调制器输出信号。 PLL根据调制器输出信号进行调频，并提供FM信号。 FM发射机还可以包括增益/相位补偿单元和缩放单元。 补偿单元可以补偿PLL的闭环响应的调制信号。 缩放单元可以基于增益来调整调制信号的幅度，以获得FM信号的目标频率偏差。 PLL可以以发送模式或接收模式工作，可以在发送模式下执行频率调制，并且可以在接收模式下以固定频率提供本地振荡器（LO）信号。

公开(公告)号：US07994870B2

公开(公告)日：2011-08-09

申请号：US12254155

申请日：2008-10-20

Applicant: Cheng-Han Wang ,  Tzu-wang Pan

Inventor： Cheng-Han Wang ,  Tzu-wang Pan

IPC: H03L7/00

CPC classification number: H03H11/1291 ,  H03H11/1256

Abstract: An apparatus includes a filter and a gain control circuit. The filter receives and filters an input signal and provides an output signal in a first mode and operates as part of an oscillator in a second mode. The gain control circuit varies the amplitude of an oscillator signal from the oscillator in the second mode, e.g., by adjusting at least one variable gain element within the oscillator to obtain a target amplitude and/or non rail-to-rail signal swing for the oscillator signal. The apparatus may further include a bandwidth control circuit to adjust the bandwidth of the filter in the second mode. The bandwidth control circuit receives the oscillator signal, determines a target oscillation frequency corresponding to a selected bandwidth for the filter, and adjusts at least one circuit element within the filter to obtain the target oscillation frequency.

Abstract translation: 一种装置包括滤波器和增益控制电路。 滤波器接收并过滤输入信号并在第一模式中提供输出信号，并且在第二模式中作为振荡器的一部分进行操作。 增益控制电路在第二模式中改变来自振荡器的振荡器信号的振幅，例如，通过调整振荡器内的至少一个可变增益元件以获得目标振幅和/或非轨至轨信号摆动 振荡器信号。 该装置还可以包括带宽控制电路，以在第二模式中调整滤波器的带宽。 带宽控制电路接收振荡器信号，确定与滤波器的选定带宽对应的目标振荡频率，并调整滤波器内的至少一个电路元件以获得目标振荡频率。

公开(公告)号：US20100273442A1

公开(公告)日：2010-10-28

申请号：US12430106

申请日：2009-04-26

Applicant: Yi Zeng ,  Tzu-wang Pan ,  I-Hsiang Lin ,  Jeremy Dunworth ,  Pushp Trikha ,  Rahul Apte

Inventor： Yi Zeng ,  Tzu-wang Pan ,  I-Hsiang Lin ,  Jeremy Dunworth ,  Pushp Trikha ,  Rahul Apte

IPC: H04B1/16

CPC classification number: H04B1/1027

Abstract: A frequency synthesizer within an FM receiver employs a Phase-Locked Loop (PLL) to generate a Local Oscillator (LO) signal. The LO signal is supplied to a mixer. The FM receiver also includes jammer detection functionality. If no jammer is detected, then the loop bandwidth of the PLL is set to have a relatively high value, thereby favoring suppression of in-band residual FM. If a jammer is detected, then the loop bandwidth of the PLL is set to have a relatively low value, thereby favoring suppression of out-of-band SSB phase noise. By adaptively changing loop bandwidth depending on whether a jammer is detected, performance requirements on sub-circuits within the PLL can be relaxed while still satisfying in-band residual FM and out-of-band SSB phase noise requirements. By allowing the VCO of the PLL to generate more phase noise due to the adaptive changing of loop bandwidth, VCO power consumption can be reduced.

Abstract translation: FM接收机内的频率合成器采用锁相环（PLL）来产生本地振荡器（LO）信号。 LO信号提供给混频器。 FM接收机还包括干扰检测功能。 如果没有检测到干扰，则PLL的环路带宽被设置为具有相对较高的值，从而有利于抑制带内剩余FM。 如果检测到干扰，则将PLL的环路带宽设置为具有相对较低的值，从而有利于抑制带外SSB相位噪声。 通过根据是否检测到干扰信号来自适应地改变环路带宽，可以放宽PLL内的子电路的性能要求，同时仍然满足带内剩余FM和带外SSB相位噪声要求。 通过允许PLL的VCO由于环路带宽的自适应变化而产生更多的相位噪声，可以降低VCO的功耗。