公开(公告)号：US07796682B2

公开(公告)日：2010-09-14

申请号：US12476207

申请日：2009-06-01

Applicant: Abbas Amirichimeh ,  Howard Baumer ,  John Louie ,  Vasudevan Parthasarathy ,  Linda Ying

Inventor： Abbas Amirichimeh ,  Howard Baumer ,  John Louie ,  Vasudevan Parthasarathy ,  Linda Ying

IPC: H04L25/20 ,  H04L7/00 ,  H04B1/38

CPC classification number: H03K5/135 ,  H04L7/0012 ,  H04L7/0091

Abstract: A transceiver system is disclosed that includes a plurality of transceiver chips. Each transceiver chip includes one or more SERDES cores. Each SERDES core includes one or more SERDES lanes. Each SERDES lane includes a receive channel and a transmit channel. The transmit channel of each SERDES lane is phase-locked with a corresponding receive channel. The transceiver system has the capability of phase-locking a transmit clock signal phase of a transmitting component with a receive clock signal phase of a receiving component that is a part of a different SERDES lane, a different SERDES core, a different substrate, or even a different board. Each SERDES core receives and transmits data to and from external components connected to the SERDES core, such as hard disk drives. A method of transferring data from a first external component coupled to a receive channel to a second external component coupled to a transmit channel is also disclosed.

Abstract translation: 公开了一种收发器系统，其包括多个收发器芯片。 每个收发器芯片包括一个或多个SERDES内核。 每个SERDES核心包​​括一个或多个SERDES通道。 每个SERDES通道包括接收通道和发送通道。 每个SERDES通道的发送通道与相应的接收通道锁相。 收发器系统具有将发送部件的发送时钟信号相位锁定在接收部件的接收时钟信号相位的能力，该接收时钟信号相位是不同SERDES通道的一部分的接收时钟信号相位，不同的SERDES内核，不同的基板，甚至是 一个不同的董事会。 每个SERDES核心接收和传输连接到SERDES核心的外部组件（例如硬盘驱动器）的数据。 还公开了将数据从耦合到接收信道的第一外部组件传送到耦合到发射信道的第二外部组件的方法。

公开(公告)号：US07630446B2

公开(公告)日：2009-12-08

申请号：US12222367

申请日：2008-08-07

Applicant: Vasudevan Parthasarathy

Inventor： Vasudevan Parthasarathy

IPC: H04B3/00 ,  H04B1/38

CPC classification number: H04L25/0272 ,  H04L25/02 ,  H04L25/0292

Abstract: An automatic polarity swap is implemented in a communications system. Two or more transceivers having differential inputs and outputs are coupled together through an interface, such as a backplane to form a communications system. In such a configuration, it is possible to cross-connect the differential data lines or signals at the interface, which will cause invalid data words to received at the second transceiver. Accordingly, the present invention includes an error check and correction module that detects invalid data words after parallel-to-serial conversion. More specifically, an error check determines if the parallel differential signal represents a valid data word. This can be done, for example, by storing and comparing valid data words in a memory such as RAM. If the received data word is valid, then no corrective action is taken. However, if the received data word is invalid, then the parallel differential signal is inverted using a logic circuit, which will correct the error if it is due to cross-connection of the differential lines at the interface or anywhere else.

Abstract translation: 在通信系统中实现自动极性交换。 具有差分输入和输出的两个或多个收发器通过诸如背板的接口耦合在一起以形成通信系统。 在这种配置中，可以将接口处的差分数据线或信号交叉连接，这将导致在第二收发器处接收的无效数据字。 因此，本发明包括在并行到串行转换之后检测无效数据字的错误检查和校正模块。 更具体地，错误检查确定并行差分信号是否表示有效的数据字。 这可以通过例如存储和比较诸如RAM的存储器中的有效数据字来完成。 如果接收到的数据字有效，则不采取任何纠正措施。 然而，如果接收到的数据字无效，则使用逻辑电路对并行差分信号进行反相，如果由于差分线在接口或其他任何地方的交叉连接，则将纠正错误。

公开(公告)号：US20090113258A1

公开(公告)日：2009-04-30

申请号：US11977694

申请日：2007-10-25

Applicant: Vasudevan Parthasarathy

Inventor： Vasudevan Parthasarathy

IPC: G01R31/28

CPC classification number: G01R31/31716 ,  H04L43/50

Abstract: There is provided a method of testing a first device using a tester. The method comprises receiving test data having a pattern by the first device from the tester; detecting the pattern of the test data by the first device; generating first data, by the first device, according to the pattern detected by the detecting; comparing the test data with the pattern detected by the detecting; determining errors in the test data, by the first device, based on the comparing; inserting the errors into the first data to generate error-inserted first data; and transmitting the error-inserted first data by the first device to the tester. The method may further comprise generating a first clock at the first device; wherein the transmitting uses the first clock for transmitting the error-inserted first data.

Abstract translation: 提供了使用测试仪测试第一设备的方法。 该方法包括从测试器接收第一设备具有图案的测试数据; 由第一设备检测测试数据的模式; 根据检测到的图案，由第一装置产生第一数据; 将测试数据与通过检测检测到的模式进行比较; 基于所述比较，确定由所述第一装置测试数据中的误差; 将错误插入到第一数据中以产生错误插入的第一数据; 以及将所述第一设备的错误插入的第一数据发送给所述测试器。 该方法还可以包括在第一设备处产生第一时钟; 其中所述发送使用所述第一时钟来发送所述错误插入的第一数据。

公开(公告)号：US20080069199A1

公开(公告)日：2008-03-20

申请号：US11845779

申请日：2007-08-27

Applicant: Chung-Jue Chen ,  Vasudevan Parthasarathy ,  Sudeep Bhoja

Inventor： Chung-Jue Chen ,  Vasudevan Parthasarathy ,  Sudeep Bhoja

IPC: H03H7/30

CPC classification number: H04L25/061 ,  H04L25/03057 ,  H04L2025/03547

Abstract: Embodiments include a decision feedback equalizer (DFE) that includes a first comparator configured to receive as inputs a soft value and a first threshold, a second comparator configured to receive as inputs the soft value and a second threshold, a selector configured to select an output of either the first comparator or the second comparator as a DFE output based on one or more previous bits output by the selector; an error calculator configured to determine an error for the first comparator and the second comparator, and a threshold adjuster configured to adjust the first threshold and the second threshold, the first threshold and the second threshold each being a non-linear combination of one or more previous outputs of the selector.

Abstract translation: 实施例包括判决反馈均衡器（DFE），其包括被配置为接收软值和第一阈值作为输入的第一比较器，被配置为接收软值和第二阈值作为输入的第二比较器，被配置为选择输出 基于由选择器输出的一个或多个以前的位，作为DFE输出的第一比较器或第二比较器; 配置为确定第一比较器和第二比较器的误差的误差计算器以及被配置为调整第一阈值和第二阈值的阈值调整器，第一阈值和第二阈值各自是一个或多个的非线性组合 选择器的先前输出。

公开(公告)号：US07263141B1

公开(公告)日：2007-08-28

申请号：US09391059

申请日：1999-09-07

Applicant: Vasudevan Parthasarathy ,  Kumar Ramaswamy ,  John Sidney Stewart

Inventor： Vasudevan Parthasarathy ,  Kumar Ramaswamy ,  John Sidney Stewart

IPC: H03D1/00 ,  H03M13/03

CPC classification number: H03M13/256 ,  H03M13/3776 ,  H03M13/3961 ,  H03M13/4107 ,  H03M13/4169 ,  H03M13/6508

Abstract: A trellis decoder system uses a feed-forward trellis demapping configuration to prevent error propagation. In a system for processing encoded binary data symbols representable as a symbol constellation, a decoder includes a delay for delaying received encoded symbol data. The decoder also includes a re-encoder for re-coding decoded symbol representative data and a processor for deriving decoded symbol data. The processor derives decoded symbol data using the delayed encoded symbol data and re-encoded data representative of a difference between successive symbols computed using an error propagation-free, feed-forward configuration.

Abstract translation: 网格解码器系统使用前馈网格解映射配置来防止错误传播。 在用于处理可表示为符号星座的编码二进制数据符号的系统中，解码器包括用于延迟接收的编码符号数据的延迟。 解码器还包括用于重新编码解码的符号代表数据的重新编码器和用于导出解码符号数据的处理器。 处理器使用延迟编码的符号数据和代表使用无差错传播的前馈配置计算的连续符号之间的差异的重新编码的数据来导出解码的符号数据。

公开(公告)号：US20060251195A1

公开(公告)日：2006-11-09

申请号：US11124598

申请日：2005-05-05

Applicant: Chung-Jue Chen ,  Vasudevan Parthasarathy ,  Afshin Momtaz ,  Hong Chen

Inventor： Chung-Jue Chen ,  Vasudevan Parthasarathy ,  Afshin Momtaz ,  Hong Chen

IPC: H04B1/10

CPC classification number: H04L25/03057 ,  H04L2025/03687

Abstract: Data error such as mean square error may be reduced in a system such as a communication receiver using a dithering algorithm that adjusts one or more parameters in the system. The dithering algorithm may be applied to more than one parameter. The dithering algorithm may include a state machine to alter the rate of change dependent on the state of the dithering algorithm.

Abstract translation: 在诸如使用调整系统中的一个或多个参数的抖动算法的通信接收机的系统中，诸如均方误差之类的数据误差可能会降低。 抖动算法可以应用于多个参数。 抖动算法可以包括状态机来改变取决于抖动算法的状态的变化率。

公开(公告)号：US08661309B2

公开(公告)日：2014-02-25

申请号：US13014519

申请日：2011-01-26

Applicant: William Bliss ,  Vasudevan Parthasarathy

Inventor： William Bliss ,  Vasudevan Parthasarathy

IPC: H03M13/00

CPC classification number: H03M13/151 ,  H03M13/05 ,  H03M13/1515 ,  H04B7/0456 ,  H04L1/0041 ,  H04L1/0045 ,  H04L1/0057 ,  H04L25/03949 ,  H04L25/4917 ,  H04L27/00 ,  H04L27/02

Abstract: In conventional Backplane Ethernet systems, data is transmitted over two pairs of copper traces in one direction using a PAM-2 scheme and a baud rate of 10.3125 GHz, giving an effective bit rate of 10.3125 Gbps. The rate at which data can be transmitted in Backplane Ethernet systems, while still being reliably received, is typically limited by ISI caused by the dispersive nature of the copper traces, frequency dependent transmission losses caused primarily by skin effect and dielectric loss of the copper traces, and cross-talk from adjacent communication lines. The present invention is directed to systems for overcoming these and other signal impairments to achieve speeds up to, and beyond, twice the conventional 10 Gbps limit associated with Backplane Ethernet systems.

Abstract translation: 在传统的背板以太网系统中，使用PAM-2方案和10.3125 GHz的波特率，通过两对铜线路在一个方向上传输数据，提供10.3125 Gbps的有效比特率。 在背板以太网系统中数据传输的速率仍然可靠地接收，通常受到铜迹线色散性质引起的ISI的限制，主要由皮肤效应引起的频率依赖传输损耗和铜迹线的介电损耗 ，以及相邻通信线路的串扰。 本发明涉及用于克服这些和其他信号损伤的系统，以实现高达和超过与背板以太网系统相关联的常规10Gbps限制的两倍的速度。

公开(公告)号：US20120201280A1

公开(公告)日：2012-08-09

申请号：US13367282

申请日：2012-02-06

Applicant: Abbas AMIRICHIMEH ,  Howard Baumer ,  John Louie ,  Vasudevan Parthasarathy ,  Linda Ying

Inventor： Abbas AMIRICHIMEH ,  Howard Baumer ,  John Louie ,  Vasudevan Parthasarathy ,  Linda Ying

IPC: H04B1/38

CPC classification number: H03K5/135 ,  H04L7/0012 ,  H04L7/0091

Abstract: A transceiver system is disclosed that includes a plurality of transceiver chips. Each transceiver chip includes one or more SERDES cores. Each SERDES core includes one or more SERDES lanes. Each SERDES lane includes a receive channel and a transmit channel. The transmit channel of each SERDES lane is phase-locked with a corresponding receive channel. The transceiver system has the capability of phase-locking a transmit clock signal phase of a transmitting component with a receive clock signal phase of a receiving component that is a part of a different SERDES lane, a different SERDES core, a different substrate, or even a different board. Each SERDES core receives and transmits data to and from external components connected to the SERDES core, such as hard disk drives. A method of transferring data from a first external component coupled to a receive channel to a second external component coupled to a transmit channel is also disclosed.

Abstract translation: 公开了一种收发器系统，其包括多个收发器芯片。 每个收发器芯片包括一个或多个SERDES内核。 每个SERDES核心包​​括一个或多个SERDES通道。 每个SERDES通道包括接收通道和发送通道。 每个SERDES通道的发送通道与相应的接收通道锁相。 收发器系统具有将发送部件的发送时钟信号相位锁定在接收部件的接收时钟信号相位的能力，该接收时钟信号相位是不同SERDES通道的一部分的接收时钟信号相位，不同的SERDES内核，不同的基板，甚至是 一个不同的董事会。 每个SERDES核心接收和传输连接到SERDES核心的外部组件（例如硬盘驱动器）的数据。 还公开了将数据从耦合到接收信道的第一外部组件传送到耦合到发射信道的第二外部组件的方法。

公开(公告)号：US20090232192A1

公开(公告)日：2009-09-17

申请号：US12476207

申请日：2009-06-01

Applicant: Abbas AMIRICHIMEH ,  Howard Baumer ,  John Louie ,  Vasudevan Parthasarathy ,  Linda Ying

Inventor： Abbas AMIRICHIMEH ,  Howard Baumer ,  John Louie ,  Vasudevan Parthasarathy ,  Linda Ying

IPC: H04B1/38

CPC classification number: H03K5/135 ,  H04L7/0012 ,  H04L7/0091

Abstract: A transceiver system is disclosed that includes a plurality of transceiver chips. Each transceiver chip includes one or more SERDES cores. Each SERDES core includes one or more SERDES lanes. Each SERDES lane includes a receive channel and a transmit channel. The transmit channel of each SERDES lane is phase-locked with a corresponding receive channel. The transceiver system has the capability of phase-locking a transmit clock signal phase of a transmitting component with a receive clock signal phase of a receiving component that is a part of a different SERDES lane, a different SERDES core, a different substrate, or even a different board. Each SERDES core receives and transmits data to and from external components connected to the SERDES core, such as hard disk drives. A method of transferring data from a first external component coupled to a receive channel to a second external component coupled to a transmit channel is also disclosed.

Abstract translation: 公开了一种收发器系统，其包括多个收发器芯片。 每个收发器芯片包括一个或多个SERDES内核。 每个SERDES核心包​​括一个或多个SERDES通道。 每个SERDES通道包括接收通道和发送通道。 每个SERDES通道的发送通道与相应的接收通道锁相。 收发器系统具有将发送部件的发送时钟信号相位锁定在接收部件的接收时钟信号相位的能力，该接收时钟信号相位是不同SERDES通道的一部分的接收时钟信号相位，不同的SERDES内核，不同的基板，甚至是 一个不同的董事会。 每个SERDES核心接收和传输连接到SERDES核心的外部组件（例如硬盘驱动器）的数据。 还公开了将数据从耦合到接收信道的第一外部组件传送到耦合到发射信道的第二外部组件的方法。

公开(公告)号：US20080212665A1

公开(公告)日：2008-09-04

申请号：US12071138

申请日：2008-02-15

Applicant: Jay Proano ,  Howard Baumer ,  Chung-Jue Chen ,  Ali Ghiasi ,  Vasudevan Parthasarathy ,  Rajesh Satapathy ,  Linda Ying

Inventor： Jay Proano ,  Howard Baumer ,  Chung-Jue Chen ,  Ali Ghiasi ,  Vasudevan Parthasarathy ,  Rajesh Satapathy ,  Linda Ying

IPC: H04B3/46 ,  H04B17/00

CPC classification number: H04L43/0823

Abstract: A system is presented that monitors the quality of a communications channel with mirror receivers. A first receiver and a second receiver, coupled in parallel with the first receiver, receive a data signal transmitted over the communications channel. The second receiver generates an output signal. A signal integrity (SI) processor manipulates the output signal in order to determine the quality of the communications channel. The SI processor samples a phase-shifted version of the output signal, which has a phase shifted relative to a zero reference phase, and analyzes the phase-shifted version of the output signal for bit errors. In an embodiment, the SI processor manipulates the output signal to extract an eye diagram indicative of the quality of the communications channel. The SI processor non-intrusively determines the quality of the communications channel using the second receiver.

Abstract translation: 提出了一种监控带有镜像接收器的通信通道质量的系统。 与第一接收机并联耦合的第一接收机和第二接收机接收通过通信信道发送的数据信号。 第二个接收器产生一个输出信号。 信号完整性（SI）处理器操纵输出信号，以便确定通信信道的质量。 SI处理器对输出信号的相移版本进行采样，该相位版本相对于零参考相位具有相移，并且分析用于位错误的输出信号的相移版本。 在一个实施例中，SI处理器操纵输出信号以提取指示通信信道质量的眼图。 SI处理器非侵入性地确定使用第二接收机的通信信道的质量。