公开(公告)号：US20160282921A1

公开(公告)日：2016-09-29

申请号：US14754475

申请日：2015-06-29

Applicant: Vijay Kumar KODAVALLA

Inventor： Vijay Kumar KODAVALLA

IPC: G06F1/32

CPC classification number: G06F1/324 ,  H03L7/10 ,  H03L7/18 ,  H04B15/02 ,  H04B2215/065 ,  Y02D10/126

Abstract: This disclosure relates generally to a host-peripheral interface, and more particularly to system and method for dynamically adjusting a low power clock frequency of a host device upon detecting coupling of a peripheral device to the host device. In one embodiment, a method is provided for dynamically adjusting a low power clock frequency of a host device. The method comprises dynamically determining an initial frequency of a low power clock of the host device at which a low power link between the host device and a peripheral device is operational, computing a low power clock frequency range of the host device based on the initial frequency of the low power clock, assessing the low power link in the low power clock frequency range, and adjusting the low power clock frequency to a typical frequency of the low power clock frequency range based on the assessment.

Abstract translation: 本公开一般涉及主机 - 外设接口，更具体地涉及用于在检测到外围设备耦合到主机设备时动态调整主机设备的低功率时钟频率的系统和方法。 在一个实施例中，提供了一种用于动态调整主机设备的低功率时钟频率的方法。 该方法包括动态地确定主机设备的低功率时钟的初始频率，在主机设备和外围设备之间的低功率链路可操作的初始频率，基于初始频率计算主机设备的低功率时钟频率范围 评估低功率时钟频率范围内的低功率链路，并根据评估将低功率时钟频率调整到低功率时钟频率范围的典型频率。

公开(公告)号：US09209836B2

公开(公告)日：2015-12-08

申请号：US14550228

申请日：2014-11-21

Applicant: Vijay Kumar Kodavalla

Inventor： Vijay Kumar Kodavalla

IPC: H03M13/00 ,  H03M13/35 ,  H03M13/29 ,  H03M13/37 ,  H04N19/136 ,  H04N19/172 ,  H04N19/192 ,  H04N19/89 ,  G06F11/07 ,  H03M13/11

CPC classification number: H03M13/353 ,  G06F11/076 ,  H03M13/1102 ,  H03M13/13 ,  H03M13/2909 ,  H03M13/3746 ,  H03M13/6312 ,  H04N19/136 ,  H04N19/172 ,  H04N19/192 ,  H04N19/89

Abstract: This disclosure generally relates to encoding, transmission, and decoding of digital video, and more particularly to methods and systems for minimizing decoding delay in distributed video coding (DVC). In one embodiment, a video decoding method is disclosed, comprising: obtaining side information; obtaining a syndrome bit chunk corresponding to a non-key-frame bit-plane; performing, via one or more processors, at least one non-key-frame bit-plane channel decoding iteration using the side information and the syndrome bit chunk; generating a decoded bit-plane via performing the at least one non-key-frame bit-plane channel decoding iteration; determining a bit error rate measure for the decoded bit-plane; determining, based on the bit error rate measure, a number of additional syndrome bit chunks to request; and providing a request for the additional syndrome bit chunks.

Abstract translation: 本公开一般涉及数字视频的编码，传输和解码，更具体地涉及用于最小化分布式视频编码（DVC）中解码延迟的方法和系统。 在一个实施例中，公开了一种视频解码方法，包括：获得边信息; 获得对应于非关键帧位平面的校正子位块; 通过一个或多个处理器，使用所述侧面信息和所述综合征位块执行至少一个非关键帧位平面信道解码迭代; 通过执行所述至少一个非关键帧位平面信道解码迭代来生成解码位平面; 确定解码位平面的误码率测量; 基于比特误差率测量确定要请求的多个附加的综合比特块; 并提供对附加综合征位块的请求。

公开(公告)号：US20150278418A1

公开(公告)日：2015-10-01

申请号：US14283454

申请日：2014-05-21

Applicant: Vijay Kumar KODAVALLA

Inventor： Vijay Kumar KODAVALLA

IPC: G06F17/50

CPC classification number: G06F17/5054 ,  G06F2217/14

Abstract: The present disclosure relates to methods and related systems and computer-readable mediums. The methods include receiving a design for a programmable logic device (PLD). The design includes a plurality of nodes. The method also includes modifying, via one or more hardware processors, the design to include a logic analyzer circuit. The logic analyzer circuit includes inputs for a plurality of selectable groups of capture signals for connecting to selected nodes of the plurality of nodes. In addition, the method includes outputting the design to the PLD to program the PLD. The disclosure also relates a system comprising a user logic circuit, a logic analyzer circuit, and a memory.

Abstract translation: 本公开涉及方法和相关系统以及计算机可读介质。 这些方法包括接收可编程逻辑器件（PLD）的设计。 该设计包括多个节点。 该方法还包括通过一个或多个硬件处理器修改包括逻辑分析器电路的设计。 逻辑分析器电路包括用于多个可选择的捕获信号组的输入，用于连接到多个节点中的选定节点。 此外，该方法包括将设计输出到PLD以对PLD进行编程。 本公开还涉及包括用户逻辑电路，逻辑分析器电路和存储器的系统。

公开(公告)号：US08924827B2

公开(公告)日：2014-12-30

申请号：US13752650

申请日：2013-01-29

Applicant: Vijay Kumar Kodavalla

Inventor： Vijay Kumar Kodavalla

IPC: H03M13/00 ,  H03M13/29 ,  H03M13/37

CPC classification number: H03M13/353 ,  G06F11/076 ,  H03M13/1102 ,  H03M13/13 ,  H03M13/2909 ,  H03M13/3746 ,  H03M13/6312 ,  H04N19/136 ,  H04N19/172 ,  H04N19/192 ,  H04N19/89

Abstract: This disclosure generally relates to encoding, transmission, and decoding of digital video, and more particularly to methods and systems for minimizing decoding delay in distributed video coding (DVC). In one embodiment, a video decoding method is disclosed. The video decoding method may include obtaining side information and obtaining a syndrome bit chunk corresponding to a non-key-frame bit-plane. One or more processors may perform one non-key-frame bit-plane channel decoding iteration using the side information and the syndrome bit chunk. A decoded bit-plane may be generated via performing the at least one non-key-frame bit-plane channel decoding iteration. Also, a bit error rate measure for the decoded bit-plane may be determined. A number of additional syndrome bit chunks to request may be determined based on the bit error rate measure, and the request for the additional syndrome bit chunks provided.

Abstract translation: 本公开一般涉及数字视频的编码，传输和解码，更具体地涉及用于最小化分布式视频编码（DVC）中解码延迟的方法和系统。 在一个实施例中，公开了一种视频解码方法。 视频解码方法可以包括获得边信息并获得与非关键帧位平面对应的校正子位块。 一个或多个处理器可以使用侧面信息和综合征位块执行一个非关键帧位平面信道解码迭代。 可以通过执行至少一个非关键帧位平面信道解码迭代来生成解码位平面。 此外，可以确定解码位平面的误码率测量。 可以基于比特错误率测量和提供的附加综合征位块的请求来确定要请求的多个附加的校正子位块。

公开(公告)号：US08447106B2

公开(公告)日：2013-05-21

申请号：US13442866

申请日：2012-04-10

Applicant: Vijay Kumar Kodavalla ,  Deepak Kumar Aravapalli

Inventor： Vijay Kumar Kodavalla ,  Deepak Kumar Aravapalli

IPC: G06K9/00

CPC classification number: H04N9/68 ,  G06T5/009 ,  G06T5/40 ,  G06T5/50 ,  G06T2207/10016 ,  G06T2207/10024

Abstract: System and method for dynamically and adaptively enhancing user chosen colors on a frame-by-frame basis of an incoming digital video signal using a saturation dependent value bright-gain is disclosed. In one embodiment, a value-saturation 2D-histogram for each of the user chosen colors is formed using a substantially current video frame. Further, a saturation dependent value bright-gain is dynamically computed for each of the user chosen colors using the corresponding value-saturation 2D-histogram of the substantially current video frame and corresponding value-saturation 2D-histogram information and a saturation dependent value bright-gain of a substantially previous video frame. Furthermore, which one of the dynamically computed saturation dependent value bright-gains associated with the user chosen colors to be applied on a per-pixel basis is determined. The determined saturation dependent value bright-gain is applied to value component on the per-pixel basis in the substantially current or next video frame.

Abstract translation: 公开了一种使用饱和依赖值亮度增益来逐帧地基于输入数字视频信号来动态地和适应地增强用户选择的颜色的系统和方法。 在一个实施例中，使用基本上当前的视频帧来形成每个用户选择的颜色的值饱和2D直方图。 此外，使用基本上当前的视频帧和对应的值饱和2D直方图信息的对应的值饱和2D直方图以及饱和度依赖值亮度增益来动态地计算每个用户选择的颜色的饱和度依赖值亮度增益。 获得基本上以前的视频帧。 此外，确定与以每像素为基础施加的用户选择的颜色相关联的动态计算的饱和依赖值亮度增益中的哪一个。 所确定的饱和相关值亮增益在基本上当前或下一个视频帧中以每像素为基础应用于值分量。

公开(公告)号：US20120201455A1

公开(公告)日：2012-08-09

申请号：US13442866

申请日：2012-04-10

Applicant: VIJAY KUMAR KODAVALLA ,  DEEPAK KUMAR ARAVAPALLI

Inventor： VIJAY KUMAR KODAVALLA ,  DEEPAK KUMAR ARAVAPALLI

IPC: G06K9/00

CPC classification number: H04N9/68 ,  G06T5/009 ,  G06T5/40 ,  G06T5/50 ,  G06T2207/10016 ,  G06T2207/10024

Abstract: System and method for dynamically and adaptively enhancing user chosen colors on a frame-by-frame basis of an incoming digital video signal using a saturation dependent value bright-gain is disclosed. In one embodiment, a value-saturation 2D-histogram for each of the user chosen colors is formed using a substantially current video frame. Further, a saturation dependent value bright-gain is dynamically computed for each of the user chosen colors using the corresponding value-saturation 2D-histogram of the substantially current video frame and corresponding value-saturation 2D-histogram information and a saturation dependent value bright-gain of a substantially previous video frame. Furthermore, which one of the dynamically computed saturation dependent value bright-gains associated with the user chosen colors to be applied on a per-pixel basis is determined. The determined saturation dependent value bright-gain is applied to value component on the per-pixel basis in the substantially current or next video frame.

Abstract translation: 公开了一种使用饱和依赖值亮度增益来逐帧地基于输入数字视频信号来动态地和适应地增强用户选择的颜色的系统和方法。 在一个实施例中，使用基本上当前的视频帧来形成每个用户选择的颜色的值饱和2D直方图。 此外，使用基本上当前的视频帧和对应的值饱和2D直方图信息的对应的值饱和2D直方图以及饱和度依赖值亮度增益来动态地计算每个用户选择的颜色的饱和度依赖值亮度增益。 获得基本上以前的视频帧。 此外，确定与以每像素为基础施加的用户选择的颜色相关联的动态计算的饱和依赖值亮度增益中的哪一个。 所确定的饱和相关值亮增益在基本上当前或下一个视频帧中以每像素为基础应用于值分量。

公开(公告)号：US07949907B2

公开(公告)日：2011-05-24

申请号：US11538072

申请日：2006-10-03

Applicant: Vijay Kumar Kodavalla ,  Chiranjeev Acharya

Inventor： Vijay Kumar Kodavalla ,  Chiranjeev Acharya

IPC: G06K5/04

CPC classification number: H03K19/1774 ,  H03K19/17744

Abstract: A programmable logic device is presented. The device comprises a plurality of logic elements and a plurality of I/O pins; a multiplexer and/or a de-multiplexer unit. The multiplexer and/or multiplexer unit is coupled between said logic elements and I/O pins. The device further comprises a control unit for generating control signal/s for selecting one of the inputs of the multiplexer and/or one of the outputs of the de-multiplexer. The control unit includes inputs for receiving a first clock signal, a second clock signal and indicators, said indicators being indicative of a phase skew relation amongst the clock signals. The control unit being configured for generating adaptively adjusted control signal/s according to the clock signals and indicators, said control signal/s are adaptively adjusted for eliminating impact of the phase skew amongst the clock signals.

Abstract translation: 提出了一种可编程逻辑器件。 该装置包括多个逻辑元件和多个I / O引脚; 多路复用器和/或解复用器单元。 多路复用器和/或多路复用器单元耦合在所述逻辑元件和I / O引脚之间。 该装置还包括一个控制单元，用于产生用于选择多路复用器的输入之一和/或解复用器的输出之一的控制信号。 控制单元包括用于接收第一时钟信号，第二时钟信号和指示符的输入，所述指示符指示时钟信号之间的相位偏移关系。 控制单元被配置为根据时钟信号和指示器产生自适应调整的控制信号，所述控制信号被自适应地调整，以消除时钟信号之间的相位偏移的影响。

公开(公告)号：US20090304275A1

公开(公告)日：2009-12-10

申请号：US12132615

申请日：2008-06-04

Applicant: Vijay Kumar Kodavalla ,  Deepak Kumar Aravapalli

Inventor： Vijay Kumar Kodavalla ,  Deepak Kumar Aravapalli

IPC: G06K9/00

CPC classification number: H04N9/68 ,  G06T5/009 ,  G06T5/40 ,  G06T5/50 ,  G06T2207/10016 ,  G06T2207/10024

Abstract: A method and apparatus for dynamically, adaptively and/or concurrently enhancing and diminishing of colors in digital video images is disclosed. In one embodiment, a method includes dynamically computing a saturation gain, adaptive to slow or fast moving image sequences, for each user chosen color of a substantially current video frame, dynamically computing a saturation dependent value gains, adaptive to slow or fast moving image sequences, for each user chosen color of the substantially current video frame, determining which of the dynamically computed saturation gain and a saturation dependent value gains associated with each user chosen color or no gain is to be applied on a per-pixel basis by comparing Hue, saturation and value (HSV) components of each pixel with predefined HSV ranges of various user chosen colors, respectively, and applying the determined saturation and/or saturation dependent value gain on the per-pixel basis, in the substantially current or next video frame.

Abstract translation: 公开了用于动态，自适应地和/或同时增强和减少数字视频图像中的颜色的方法和装置。 在一个实施例中，一种方法包括动态地计算针对基本上当前视频帧的每个用户选择的颜色的适应于慢或快速运动图像序列的饱和度增益，动态地计算适应慢或快速运动图像序列的饱和度依赖值增益 对于每个用户选择的基本当前视频帧的颜色，通过比较色相，确定每个像素基础上应用动态计算的饱和度增益和与每个用户选择的颜色相关联的饱和度依赖值增益或无增益， 每个像素的饱和度和值（HSV）分量分别具有各种用户选择的颜色的预定义HSV范围，并且在基本上当前的或下一个视频帧中在每像素的基础上应用所确定的饱和度和/或饱和度依赖值增益。

公开(公告)号：US09720485B2

公开(公告)日：2017-08-01

申请号：US14754475

申请日：2015-06-29

Applicant: Vijay Kumar Kodavalla

Inventor： Vijay Kumar Kodavalla

IPC: G06F1/00 ,  G06F1/32 ,  H03L7/18 ,  H03L7/10 ,  H04B15/02

CPC classification number: G06F1/324 ,  H03L7/10 ,  H03L7/18 ,  H04B15/02 ,  H04B2215/065 ,  Y02D10/126

Abstract: This disclosure relates generally to a host-peripheral interface, and more particularly to system and method for dynamically adjusting a low power clock frequency of a host device upon detecting coupling of a peripheral device to the host device. In one embodiment, a method is provided for dynamically adjusting a low power clock frequency of a host device. The method comprises dynamically determining an initial frequency of a low power clock of the host device at which a low power link between the host device and a peripheral device is operational, computing a low power clock frequency range of the host device based on the initial frequency of the low power clock, assessing the low power link in the low power clock frequency range, and adjusting the low power clock frequency to a typical frequency of the low power clock frequency range based on the assessment.

公开(公告)号：US20150278991A1

公开(公告)日：2015-10-01

申请号：US14283939

申请日：2014-05-21

Applicant: Vijay Kumar KODAVALLA

Inventor： Vijay Kumar KODAVALLA

IPC: G06T3/40 ,  G06T1/60

CPC classification number: G06T3/4023

Abstract: A method, system, and non-transitory computer-readable storage medium for image scaling is provided. In one embodiment, the method may include determining one or more filter phases based on a vertical target grid distance and a horizontal target grid distance; and scaling, by one or more hardware processors, an input image using filter coefficients corresponding to the one or more filters phases to output a target image. The horizontal target grid distance may be based on a ratio of a number of horizontal filter phases and a horizontal scaling ratio, and the vertical target grid distance may be based on a ratio of a number of vertical filter phases and a vertical scaling ratio.

Abstract translation: 提供了一种用于图像缩放的方法，系统和非暂时的计算机可读存储介质。 在一个实施例中，该方法可以包括基于垂直目标网格距离和水平目标网格距离来确定一个或多个滤波器相位; 以及使用与所述一个或多个滤波器相位对应的滤波器系数，通过一个或多个硬件处理器对输入图像进行缩放以输出目标图像。 水平目标网格距离可以基于多个水平滤波器相位和水平缩放比率的比率，并且垂直目标网格距离可以基于垂直滤波器相位数和垂直缩放比率的比率。