公开(公告)号：US07685451B2

公开(公告)日：2010-03-23

申请号：US10327441

申请日：2002-12-20

Applicant: James S. Burns ,  Kenneth D. Shoemaker ,  Sudarshan Kumar ,  Tom E. Wang ,  David J. Ayers ,  Vivek Tiwari

Inventor： James S. Burns ,  Kenneth D. Shoemaker ,  Sudarshan Kumar ,  Tom E. Wang ,  David J. Ayers ,  Vivek Tiwari

IPC: G06F1/26

CPC classification number: G06F1/305

Abstract: A method and apparatus for compensating for current-change induced voltage changes is disclosed. In one embodiment, a digital throttle unit coupled to an instruction pipeline may generate a compensating current signal, which may then cause a dummy load to consume a compensating current. In another embodiment, a counter responsive to changes in clock frequency may generate a ramp current signal, which may then cause a dummy load to consume a current corresponding to the ramp current signal.

Abstract translation: 公开了一种用于补偿电流变化感应电压变化的方法和装置。 在一个实施例中，耦合到指令流水线的数字节流单元可以生成补偿电流信号，然后可以使虚拟负载消耗补偿电流。 在另一个实施例中，响应于时钟频率变化的计数器可产生斜坡电流信号，然后可以使虚拟负载消耗对应于斜坡电流信号的电流。

公开(公告)号：US07281140B2

公开(公告)日：2007-10-09

申请号：US10041092

申请日：2001-12-28

Applicant: James S. Burns ,  Stefan Rusu ,  David J. Ayers ,  Edward T. Grochowski ,  Marsha Eng ,  Vivek Tiwari

Inventor： James S. Burns ,  Stefan Rusu ,  David J. Ayers ,  Edward T. Grochowski ,  Marsha Eng ,  Vivek Tiwari

IPC: G06F1/04

CPC classification number: G06F9/3869 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/3243 ,  G06F9/3017 ,  G06F9/3873 ,  Y02D10/128 ,  Y02D10/152

Abstract: A processor includes a digital throttle to monitor the activity of various units of the processor's instruction execution pipeline. The monitored activity is scaled according to the current operating point of the processor and a power state is determined from the scaled activity. If the power state reaches a first threshold, the operating point of the processor is adjusted and a new scaling factor is selected to determine the power state.

Abstract translation: 处理器包括数字油门以监视处理器的指令执行流水线的各个单元的活动。 监视的活动根据处理器的当前工作点进行缩放，并且从缩放的活动确定功率状态。 如果功率状态达到第一阈值，则调整处理器的工作点并选择新的比例因子来确定功率状态。

公开(公告)号：US06577524B2

公开(公告)日：2003-06-10

申请号：US10228098

申请日：2002-08-27

Applicant: David M. Brooks ,  Vivek Tiwari

Inventor： David M. Brooks ,  Vivek Tiwari

IPC: G11C1900

CPC classification number: G11C7/22

Abstract: An architecture for registers and/or memory may provide a selectively disable payload portion. The architecture induced energy conservation. The architecture may include two or more payload portions for storage of payload data and a portion for storage of administrative data. Based on the contacts of the administrative data, certain payload portions may be enabled or disabled.

公开(公告)号：US06609209B1

公开(公告)日：2003-08-19

申请号：US09474461

申请日：1999-12-29

Applicant: Vivek Tiwari ,  Vinod Sharma ,  Sivakumar Makineni ,  Suri B. Medapati

Inventor： Vivek Tiwari ,  Vinod Sharma ,  Sivakumar Makineni ,  Suri B. Medapati

IPC: G06F132

CPC classification number: G06F9/3869 ,  G06F1/3228 ,  G06F1/3243 ,  G06F9/3861 ,  Y02D10/152

Abstract: A processor includes a pipeline having first and second stages and a shift register having first and second latches. An interface circuit is used to provide a clock signal from a clock signal line to the first and second stages based, at least in part, on first and second bits to be stored in the first and second latches, respectively.

Abstract translation: 处理器包括具有第一和第二级的管线和具有第一和第二锁存器的移位寄存器。 接口电路用于至少部分地基于要存储在第一和第二锁存器中的第一和第二位来从时钟信号线向第一和第二级提供时钟信号。

公开(公告)号：US06298002B1

公开(公告)日：2001-10-02

申请号：US09459904

申请日：1999-12-14

Applicant: David M. Brooks ,  Vivek Tiwari

Inventor： David M. Brooks ,  Vivek Tiwari

IPC: G11C700

CPC classification number: G11C7/22

Abstract: An architecture for registers and/or memory may provide a selectively disable payload portion. The architecture induced energy conservation. The architecture may include two or more payload portions for storage of payload data and a portion for storage of administrative data. Based on the contacts of the administrative data, certain payload portions may be enabled or disabled.