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    Method and apparatus for ensuring cell ordering in large capacity switching systems and for synchronizing the arrival time of cells to a switch fabric
    13.
    发明授权
    Method and apparatus for ensuring cell ordering in large capacity switching systems and for synchronizing the arrival time of cells to a switch fabric 有权
    用于确保大容量交换系统中的小区排序并使小区到交换结构的到达时间同步的方法和装置

    公开(公告)号：US07408959B2

    公开(公告)日：2008-08-05

    申请号：US10325701

    申请日：2002-12-18

    申请人： Martin Braff ,  Gopalakrishnan Ramamurthy ,  William J. Dally

    发明人： Martin Braff ,  Gopalakrishnan Ramamurthy ,  William J. Dally

    IPC分类号： H04J3/06

    CPC分类号： H04L12/5601 ,  H04L49/608 ,  H04L2012/5674 ,  H04L2012/5681

    摘要： Where links between a port module and plural switch fabric slices are of various lengths, a cell is transmitted from the port module to a switch fabric slice in response to a grant. The transmission is delayed by an amount based on a link round trip delay (RTD) value for the corresponding link between the port module and the switch fabric slice, and a predetermined global delay value. As a result of this delay, the cell arrives at the switch fabric slice at a fixed number of cell times (equal to the global delay value) after issuance of the grant, independent of any link lengths.

    摘要翻译： 在端口模块和多个交换矩阵切片之间的链路具有不同长度的情况下，响应于授权，小区从端口模块传输到交换矩阵切片。 基于端口模块和交换矩阵切片之间的对应链路的链路往返延迟（RTD）值和预定的全局延迟值，传输延迟一定量。 作为这种延迟的结果，独立于任何链路长度，小区在发放授权之后以固定数量的小区时间（等于全局延迟值）到达交换矩阵切片。

    Prefix search method
    14.
    发明授权
    Prefix search method 有权
    前缀搜索方式

    公开(公告)号：US07130847B2

    公开(公告)日：2006-10-31

    申请号：US10628312

    申请日：2003-07-28

    申请人： Gregory M. Waters ,  Larry R. Dennison ,  Philip P. Carvey ,  William J. Dally ,  William F. Mann

    发明人： Gregory M. Waters ,  Larry R. Dennison ,  Philip P. Carvey ,  William J. Dally ,  William F. Mann

    IPC分类号： G06F17/30

    CPC分类号： H04L45/00 ,  G06F17/30887 ,  H04L45/14 ,  H04L45/7457 ,  Y10S707/959 ,  Y10S707/99933 ,  Y10S707/99936 ,  Y10S707/99937 ,  Y10S707/99942

    摘要： Prefix searches for directing internet data packets are performed in a prefix search integrated circuit. The integrated circuit includes an array of search engines, each of which accesses a prefix search tree data structure to process a prefix search. An SDRAM is dedicated to each search engine, and SDRAMs share address and control pins to plural search engines on the IC chip. Internal nodes of the tree data structure are duplicated across banks of the SDRAMs to increase bandwidth, and leaf nodes are stored across the SDRAM banks to reduce storage requirements. Within each search engine, data stored in a data register from an SDRAM is compared to a prefix search key stored in a key register. Based on that comparison, an address is calculated to access further tree structure data from the SDRAM. Packet descriptors containing search keys are forwarded to the search engines from an input queue and the search results are forwarded to an output queue, the same packet order being maintained in the two queues.

    摘要翻译： 在前缀搜索集成电路中执行前缀搜索引导互联网数据分组。 集成电路包括搜索引擎的阵列，每个搜索引擎访问前缀搜索树数据结构以处理前缀搜索。 SDRAM专用于每个搜索引擎，并且SDRAM共享地址和控制引脚到IC芯片上的多个搜索引擎。 树状数据结构的内部节点跨越SDRAM的块复制，以增加带宽，并且叶节点存储在SDRAM存储区以减少存储要求。 在每个搜索引擎中，将存储在来自SDRAM的数据寄存器中的数据与存储在密钥寄存器中的前缀搜索键进行比较。 基于该比较，计算地址以从SDRAM访问进一步的树结构数据。 包含搜索键的分组描述符从输入队列转发到搜索引擎，搜索结果被转发到输出队列，相同的分组顺序被保持在两个队列中。

    System and method for performing efficient conditional vector operations for data parallel architectures involving both input and conditional vector values
    15.
    发明授权
    System and method for performing efficient conditional vector operations for data parallel architectures involving both input and conditional vector values 有权
    用于对涉及输入和条件向量值的数据并行架构执行有效条件向量运算的系统和方法

    公开(公告)号：US07100026B2

    公开(公告)日：2006-08-29

    申请号：US09871301

    申请日：2001-05-30

    申请人： William J. Dally ,  Scott Rixner ,  John D. Owens ,  Ujval J. Kapasi

    发明人： William J. Dally ,  Scott Rixner ,  John D. Owens ,  Ujval J. Kapasi

    IPC分类号： G06F7/38

    CPC分类号： G06F9/3891 ,  G06F9/3001 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30072 ,  G06F9/30101 ,  G06F9/3012 ,  G06F9/3828 ,  G06F9/3842 ,  G06F9/3879 ,  G06F9/3885 ,  G06F15/8084 ,  G06F15/8092

    摘要： A processor implements conditional vector operations in which, for example, an input vector containing multiple operands to be used in conditional operations is divided into two or more output vectors based on a condition vector. Each output vector can then be processed at full processor efficiency without cycles wasted due to branch latency. Data to be processed are divided into two groups based on whether or not they satisfy a given condition by, e.g., steering each to one of two index vectors. Once the data have been segregated in this way, subsequent processing can be performed without conditional operations, processor cycles wasted due to branch latency, incorrect speculation or execution of unnecessary instructions due to predication. Other examples of conditional operations include combining one or more input vectors into a single output vector based on a condition vector, conditional vector switching, conditional vector combining, and conditional vector load balancing.

    摘要翻译： 处理器实现条件向量操作，其中例如，在条件操作中包含要使用的多个操作数的输入向量基于条件向量被划分为两个或更多个输出向量。 然后可以以全处理器效率处理每个输出向量，而不会由于分支延迟而浪费周期。 基于它们是否满足给定条件，待处理的数据被分成两组，例如通过将它们转向两个索引向量中的一个。 一旦以这种方式分离了数据，就可以执行后续处理，而无需条件操作，由于分支延迟浪费处理器周期，由于预测导致不正确的猜测或执行不必要的指令。 条件操作的其他示例包括：基于条件向量，条件向量切换，条件向量组合和条件向量负载平衡将一个或多个输入向量组合成单个输出向量。

    Low power, DC-balanced serial link transmitter
    17.
    发明授权
    Low power, DC-balanced serial link transmitter 有权
    低功耗，直流平衡串行发送器

    公开(公告)号：US07061406B1

    公开(公告)日：2006-06-13

    申请号：US11040835

    申请日：2005-01-21

    申请人： William J. Dally ,  John W. Poulton

    发明人： William J. Dally ,  John W. Poulton

    IPC分类号： H03M7/00

    CPC分类号： H04L25/4904 ,  H03M5/12

    摘要： A transmitter for a data communication system that comprises a transmission line between first and second integrated circuits. An encoder on the first integrated circuit encodes an input data stream to produce a sequence of codewords, wherein codewords in the sequence are members of a set of codewords representing data in the input data stream, and the members of the set are substantially DC balanced, such as a Manchester encoded symbol set. An integrating circuit on the second integrated circuit integrates codewords by integrating for a first interval with a positive polarity within a particular signaling cell, and integrating for a second interval with a negative polarity within the particular signaling cell, to produce output representing the codewords. A sense circuit produces an output data stream.

    摘要翻译： 一种用于数据通信系统的发射机，包括第一和第二集成电路之间的传输线。 第一集成电路上的编码器对输入数据流进行编码以产生码字序列，其中该序列中的码字是表示输入数据流中的数据的一组码字的成员，并且该组的成员基本上是直流平衡的， 如曼彻斯特编码符号集。 第二集成电路上的积分电路通过将特定信令单元内的正极性的第一间隔积分并且在特定信令单元内积分具有负极性的第二间隔，从而产生表示码字的输出来对码字进行积分。 感测电路产生输出数据流。

    High-speed, low-power crossbar switch
    18.
    发明授权
    High-speed, low-power crossbar switch 失效
    高速，低功率交叉开关

    公开(公告)号：US06965299B1

    公开(公告)日：2005-11-15

    申请号：US09625802

    申请日：2000-07-26

    申请人： William J. Dally ,  Daniel K. Hartman

    发明人： William J. Dally ,  Daniel K. Hartman

    IPC分类号： G06F13/40 ,  H04L12/50

    CPC分类号： G06F13/4009

    摘要： In a crosspoint switch, both input buses and output buses are driven at low swing. Self-timed, differential, push-pull, low swing driver circuits drive the input buses and are provided in the crosspoints to drive the output buses. Clocked, regenerative sense amplifiers are provided in crosspoints and at outputs of the data buses.

    摘要翻译： 在交叉点开关中，输入总线和输出总线均以低摆幅驱动。 自定时，差分，推挽，低回转驱动电路驱动输入总线，并在交叉点提供驱动输出总线。 在数据总线的交叉点和输出端提供了时钟的再生感测放大器。

    High-speed, low-power inter-chip transmission system
    19.
    发明授权
    High-speed, low-power inter-chip transmission system 有权
    高速，低功耗的片内传输系统

    公开(公告)号：US06614268B2

    公开(公告)日：2003-09-02

    申请号：US10172535

    申请日：2002-06-13

    申请人： William J. Dally ,  Daniel K. Hartman

    发明人： William J. Dally ,  Daniel K. Hartman

    IPC分类号： G01R1900

    CPC分类号： G11C7/1084 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078

    摘要： In an integrated circuit, a data link relies on low swing differential signals. A push-pull driver circuit and a receiver circuit are both clocked from a common on-chip clock. A driver circuit includes an H-bridge of NMOS transistors and a line-to-line precharge circuit which reduces the power requirements of the circuit. A clocked repeater within the link may itself comprise a clocked receiver and an H-bridge driver with line-to-line precharge.

    摘要翻译： 在集成电路中，数据链路依赖于低摆幅差分信号。 推挽式驱动器电路和接收器电路均由公共片上时钟计时。 驱动器电路包括NMOS晶体管的H桥和减少电路的功率需求的线间预充电电路。 链路内的时钟中继器本身可以包括时钟接收器和具有线间预充电的H桥驱动器。

    Apparatus and methods for connecting modules using remote switching
    20.
    发明授权
    Apparatus and methods for connecting modules using remote switching 有权

    公开(公告)号：US06606656B2

    公开(公告)日：2003-08-12

    申请号：US09765138

    申请日：2001-01-18

    申请人： Philip P. Carvey ,  William J. Dally ,  Larry R. Dennison

    发明人： Philip P. Carvey ,  William J. Dally ,  Larry R. Dennison

    IPC分类号： G06F15177

    CPC分类号： G06F15/17343 ,  G06F15/8023

    摘要： A module connection assembly connects modules in a torus configuration that can be changed remotely. In particular, a single module can be added to or deleted from the configuration by remotely switching from conducting paths that provide end-around electrical paths to conducting paths that provide pass-through electrical paths. The assembly includes two backplanes, a first set of module connectors for electrically connecting modules to one of the backplanes, and a second set of module connectors for electrically connecting modules to the other backplane. The assembly further includes configuration controllers. Each configuration controller selects between end-around electrical paths that electrically connect multiple module connectors of the first set to each other, and pass-through electrical paths that electrically connect module connectors of the first set to module connectors of the second set. Each configuration controller operates as a remotely configurable switch that configures a topology formed by the backplanes and the module connectors. In particular, by adding a single module, the topology can be expanded incrementally.