公开(公告)号：US20080115098A1

公开(公告)日：2008-05-15

申请号：US11595151

申请日：2006-11-09

申请人： Chao-Kai Chang ,  Chia-Chi Chu ,  Wu-Shiung Feng

发明人： Chao-Kai Chang ,  Chia-Chi Chu ,  Wu-Shiung Feng

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/505 ,  G06F2217/08 ,  G06F2217/62

摘要： A method of designing a synchronous circuit of VLSI for Clock Skew scheduling and optimization is used to optimize the skew of a digital synchronous VLSI system and formulize the issue of skew optimization into the issue of quadratic equation programming. For estimation of reliability, a quadratic equation cost function is used to analyze an ideal value of skew and an error between feasible solutions. During operation, several algorithms are used to speed up the operation and lower the complexity, and ISCAS'89 is used as a testing circuit.

摘要翻译： 用于设计用于时钟偏移调度和优化的VLSI的同步电路的方法来优化数字同步VLSI系统的偏移，并将偏差优化的问题公式化为二次方程式编程的问题。 为了估计可靠性，使用二次方程成本函数来分析理想的偏差值和可行解之间的误差。 在运行过程中，使用几种算法来加快运算速度，降低复杂度，而ISCAS89则用作测试电路。

公开(公告)号：US07254790B2

公开(公告)日：2007-08-07

申请号：US10889795

申请日：2004-07-13

申请人： Herng-Jer Lee ,  Chia-Chi Chu ,  Wu-Shiung Feng ,  Ming-Hong Lai

发明人： Herng-Jer Lee ,  Chia-Chi Chu ,  Wu-Shiung Feng ,  Ming-Hong Lai

IPC分类号： G06F17/50 ,  G06F17/10

CPC分类号： G06F17/5036

摘要： A moment computation technique for general lumped R(L)C interconnect circuits with multiple resistor loops is proposed. Using the concept of tearing, a lumped R(L)C network can be partitioned into a spanning tree and several resistor links. The contributions of network moments from each free and the corresponding links can be determined independently. By combining the conventional moment computation algorithms and the reduced ordered binary decision diagram (ROBDD), the proposed method can compute system moments efficiently. Experimental results demonstrate that the proposed method can indeed obtain accurate moments and is more efficient than the conventional approach.

摘要翻译： 提出了具有多个电阻环路的一般集总R（L）C互连电路的矩计算技术。 集中R（L）C网络使用撕裂概念可以划分为生成树和几个电阻链路。 每个空闲网络时刻的贡献和相应的链接可以独立确定。 通过组合常规力矩计算算法和减少二阶决策图（ROBDD），提出的方法可以有效地计算系统时间。 实验结果表明，所提出的方法确实可以获得准确的时刻，并且比常规方法更有效。

公开(公告)号：US07216322B2

公开(公告)日：2007-05-08

申请号：US10935670

申请日：2004-09-07

申请人： Ming-Hong Lai ,  Chao-Kai Chang ,  Chia-Chi Chu ,  Wu-Shiung Feng

发明人： Ming-Hong Lai ,  Chao-Kai Chang ,  Chia-Chi Chu ,  Wu-Shiung Feng

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F1/10 ,  G06F1/32 ,  G06F17/5068 ,  G06F2217/62 ,  G06F2217/78 ,  G06F2217/84

摘要： A method for low power clock tree synthesis using buffer insertion, removal and resizing for high-speed VLSI design is proposed. A developed tool can be embedded in the existing clock tree synthesis design flow to ensure satisfying both specifying database constrains and clock skew constrains. For a given clock tree netlist, location information of buffers, parameters of wires and buffers' timing and power library are all included. Buffer delay and wire delay of the given clock tree netlist are calculated first. Then, a feasible solution is solved if an input netlist is not feasible for given constrains. Finally, a modified low power clock tree netlist, which satisfies timing specifications, is obtained using the proposed method.

摘要翻译： 提出了一种低速时钟树合成方法，用于高速VLSI设计的缓冲插入，去除和调整大小。 开发的工具可以嵌入到现有的时钟树合成设计流程中，以确保满足指定数据库约束和时钟偏移约束的要求。 对于给定的时钟树网络表，缓冲区的位置信息，导线参数和缓冲区的时序和功率库都包括在内。 首先计算给定时钟树网表的缓冲延迟和线延迟。 然后，如果输入网表对于给定的约束是不可行的，则解决可行的解决方案。 最后，使用提出的方法获得满足定时规范的修改后的低功率时钟树网表。

公开(公告)号：US07191418B2

公开(公告)日：2007-03-13

申请号：US10889510

申请日：2004-07-12

申请人： Herng-Jer Lee ,  Chia-Chi Chu ,  Wu-Shiung Feng

发明人： Herng-Jer Lee ,  Chia-Chi Chu ,  Wu-Shiung Feng

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F2217/62

摘要： A method and apparatus for rapidly selecting types of buffers which are inserted in the clock tree for high-speed VLSI design is disclosed. The developed tool can be embedded in the existing clock tree synthesis design flow to ensure minimizing the clock delay and satisfying the clock skew constrains. Given the clock tree netlist, the inserted buffers location information, the wire electrical parameters and a buffers timing library, the components delay (buffer delay and wire delay) of the clock tree can be calculated first. Then, for each I/O pin, the path delay, the clock delay and the clock skew can be obtained. Finally, using the method, a modified clock tree netlist satisfying the timing specifications can be constructed.

摘要翻译： 公开了一种用于快速选择插入时钟树中用于高速VLSI设计的缓冲器类型的方法和装置。 开发的工具可以嵌入到现有的时钟树合成设计流程中，以确保最小化时钟延迟并满足时钟偏移约束。 给定时钟树网表，可以首先计算插入的缓冲器位置信息，有线电气参数和缓冲器定时库，时钟树的分量延迟（缓冲延迟和线延迟）。 然后，对于每个I / O引脚，可以获得路径延迟，时钟延迟和时钟偏移。 最后，使用该方法，可以构建满足定时规范的修改的时钟树网表。

公开(公告)号：US07017130B2

公开(公告)日：2006-03-21

申请号：US10889497

申请日：2004-07-12

申请人： Herng-Jer Lee ,  Chia-Chi Chu ,  Wu-Shiung Feng ,  Ming-Hong Lai

发明人： Herng-Jer Lee ,  Chia-Chi Chu ,  Wu-Shiung Feng ,  Ming-Hong Lai

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5036

摘要： A method and verification of estimating crosstalk noise in coupled RLC interconnects with distributed line in nanometer integrated circuits is provided. In this invention, nanometer VLSI interconnects are modeled as distributed RLC coupled trees. The efficiency and the accuracy of moment computation of distributed lines can be shown that outperform those of lumped ones. The inductive crosstalk noise waveform can be accurately estimated in an efficient manner using the linear time moment computation technique in conjunction with the projection-based order reduction method. Recursive formulas of moment computations for coupled RC trees are derived with considering both self inductances and mutual inductances. Also, analytical formulas of voltage moments at each node will be derived explicitly. These formulas can be efficiently implemented for crosstalk estimations.

摘要翻译： 提供了一种在纳米级集成电路中与分布式线路连接的RLC互连中估计串扰噪声的方法和验证。 在本发明中，纳米VLSI互连被建模为分布式RLC耦合树。 可以看出，分布式线路的力矩计算的效率和精度优于集中线路。 可以使用线性时间矩计算技术结合基于投影的顺序降低方法，以有效的方式精确地估计电感串扰噪声波形。 考虑自感和互感两种情况，导出耦合RC树的力矩计算的递归公式。 此外，每个节点的电压矩的分析公式将被明确推导出来。 可以有效地实现这些公式用于串扰估计。

公开(公告)号：US20060053395A1

公开(公告)日：2006-03-09

申请号：US10935670

申请日：2004-09-07

申请人： Ming-Hong Lai ,  Chao-Kai Chang ,  Chia-Chi Chu ,  Wu-Shiung Feng

发明人： Ming-Hong Lai ,  Chao-Kai Chang ,  Chia-Chi Chu ,  Wu-Shiung Feng

IPC分类号： G06F17/50 ,  G06F1/04

CPC分类号： G06F17/5045 ,  G06F1/10 ,  G06F1/32 ,  G06F17/5068 ,  G06F2217/62 ,  G06F2217/78 ,  G06F2217/84

摘要： A method for low power clock tree synthesis using buffer insertion, removal and resizing for high-speed VLSI design is proposed. The developed tool can be embedded in the existing clock tree synthesis design flow to ensure satisfying both the specifying database constrains and the clock skew constrains. For a given clock tree netlist, the location information of buffers, the parameters of wires and the buffers' timing and power library are all included. The buffer delay and wire delay of the clock tree are calculated first. Then the feasible solution is solved if the input netlist is not feasible for the given constrains. Finally, a modified low power clock tree netlist, which satisfies the timing specifications, is obtained using our proposed method.

摘要翻译： 提出了一种低速时钟树合成方法，用于高速VLSI设计的缓冲插入，去除和调整大小。 开发的工具可以嵌入到现有的时钟树合成设计流程中，以确保满足指定数据库约束和时钟偏移约束。 对于给定的时钟树网表，缓冲区的位置信息，导线参数和缓冲区的时序和功率库都包括在内。 首先计算时钟树的缓冲延迟和线延迟。 那么如果输入网表对于给定的约束是不可行的，则解决可行解。 最后，使用我们提出的方法获得了满足时序规范的修改后的低功率时钟树网表。

公开(公告)号：US20060010406A1

公开(公告)日：2006-01-12

申请号：US10889497

申请日：2004-07-12

申请人： Herng-Jer Lee ,  Chia-Chi Chu ,  Wu-Shiung Feng ,  Ming-Hong Lai

发明人： Herng-Jer Lee ,  Chia-Chi Chu ,  Wu-Shiung Feng ,  Ming-Hong Lai

IPC分类号： G06F17/50 ,  G06F17/10

CPC分类号： G06F17/5036

摘要： A method and verification of estimating crosstalk noise in coupled RLC interconnects with distributed line in nanometer integrated circuits is provided. In this invention, nanometer VLSI interconnects are modeled as distributed RLC coupled trees. The efficiency and the accuracy of moment computation of distributed lines can be shown that outperform those of lumped ones. The inductive crosstalk noise waveform can be accurately estimated in an efficient manner using the linear time moment computation technique in conjunction with the projection-based order reduction method. Recursive formulas of moment computations for coupled RC trees are derived with considering both self inductances and mutual inductances. Also, analytical formulas of voltage moments at each node will be derived explicitly. These formulas can be efficiently implemented for crosstalk estimations.

摘要翻译： 提供了一种在纳米级集成电路中与分布式线路连接的RLC互连中估计串扰噪声的方法和验证。 在本发明中，纳米VLSI互连被建模为分布式RLC耦合树。 可以看出，分布式线路的力矩计算的效率和精度优于集中线路。 可以使用线性时间矩计算技术结合基于投影的顺序降低方法，以有效的方式精确地估计电感串扰噪声波形。 考虑自感和互感两种情况，导出耦合RC树的力矩计算的递归公式。 此外，每个节点的电压矩的分析公式将被明确推导出来。 可以有效地实现这些公式用于串扰估计。

公开(公告)号：US07600206B2

公开(公告)日：2009-10-06

申请号：US11733030

申请日：2007-04-09

申请人： Ming-Hong Lai ,  Chao-Hsuan Hsu ,  Chia-Chi Chu ,  Wu-Shiung Feng

发明人： Ming-Hong Lai ,  Chao-Hsuan Hsu ,  Chia-Chi Chu ,  Wu-Shiung Feng

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A method estimates the signal delay in a VLSI circuit and accurately estimates the delay and conversion time of a transmission signal in the circuit in order to prevent a designer of the VLSI circuit from erroneously judging the logic made by the designed circuit.

摘要翻译： 一种方法估计VLSI电路中的信号延迟，并准确估计电路中传输信号的延迟和转换时间，以防止VLSI电路的设计者错误地判断由设计电路所做的逻辑。

公开(公告)号：US20080318372A1

公开(公告)日：2008-12-25

申请号：US12199537

申请日：2008-08-27

申请人： Hsien-Chin Chiu ,  Chien-Cheng Wei ,  Wei-Hsien Lee ,  Wu-Shiung Feng

发明人： Hsien-Chin Chiu ,  Chien-Cheng Wei ,  Wei-Hsien Lee ,  Wu-Shiung Feng

IPC分类号： H01L21/8238

CPC分类号： H01L29/402 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66575 ,  H01L29/78

摘要： This invention relates to a method for making a high-linearity and high-power CMOS structure and particularly to a field plate technology that is applied to a CMOS component, in which the field plate is formed on a dielectric layer of the CMOS, being arranged above a gate and a drain. An electric field is provided to significantly improve the RF linearity and output power of the CMOS component.

摘要翻译： 本发明涉及一种用于制造高线性和高功率CMOS结构的方法，特别涉及一种应用于CMOS元件的场板技术，其中场板形成在CMOS的电介质层上，布置 在闸门和排水沟之上。 提供电场以显着地提高CMOS部件的RF线性度和输出功率。

公开(公告)号：US20070033549A1

公开(公告)日：2007-02-08

申请号：US11199026

申请日：2005-08-08

申请人： Chia-Chi Chu ,  Herng-Jer Lee ,  Wu-Shiung Feng ,  Chao-Kai Chang

发明人： Chia-Chi Chu ,  Herng-Jer Lee ,  Wu-Shiung Feng ,  Chao-Kai Chang

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： An interconnect model-order reduction method for reduction of a nano-level semiconductor interconnect network as an original interconnect network by using iteration-based Arnoldi algorithms disclosed. The method is performed based on a projection method and has become a necessity for efficient interconnect modeling and simulations. To select order of the reduced-order model that can efficiently reflect essential dynamics of the original interconnect network, a residual error between transfer functions of the original interconnect network and the reduced interconnect model may be considered as a reference in determining if the iteration process should end, analytical expressions of the residual error being derived herein. Furthermore, the approximate transfer function of the reduced interconnect model may also be expressed as an addition of the original interconnect model and some additive perturbations. A perturbation matrix is only related with resultant vectors at a previous step of the Arnoldi algorithm. Therefore, the residual error information may be taken as a reference for the order selection scheme used in Krylov subspace model-order algorithm.

摘要翻译： 一种用于通过使用基于迭代的Arnoldi算法来将纳米级半导体互连网络还原为原始互连网络的互连模型级降低方法。 该方法基于投影方法进行，并且已经成为有效的互连建模和模拟的必要条件。 为了选择可以有效地反映原始互连网络的基本动力学的简化模型的顺序，原始互连网络的传递函数与简化的互连模型之间的残差可能被认为是确定迭代过程应该如何 结束，这里得出的残差的解析表达式。 此外，还原互连模型的近似传递函数也可以表示为原始互连模型和一些附加扰动的相加。 扰动矩阵仅与Arnoldi算法前一步的合成矢量有关。 因此，剩余误差信息可以作为Krylov子空间模型顺序算法中使用的顺序选择方案的参考。