中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

248 records (took 0.025 seconds)

    MRAM diode array and access method
    11.
    发明授权
    MRAM diode array and access method 有权
    MRAM二极管阵列和访问方式

    公开(公告)号：US08289746B2

    公开(公告)日：2012-10-16

    申请号：US12948824

    申请日：2010-11-18

    Applicant: Yiran Chen ,  Hai Li ,  Hongyue Liu ,  Yong Lu ,  Song S. Xue

    Inventor： Yiran Chen ,  Hai Li ,  Hongyue Liu ,  Yong Lu ,  Song S. Xue

    IPC: G11C5/08 ,  G11C27/00 ,  G11C11/00

    CPC classification number: G11C11/1675 ,  G11C11/1659

    Abstract: A memory unit includes a magnetic tunnel junction data cell is electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel junction data cell. A first diode is electrically between the magnetic tunnel junction data cell and the source line and a second diode is electrically between the magnetic tunnel junction data cell and the source line. The first diode and second diode are in parallel electrical connection, and having opposing forward bias directions. The memory unit is configured to be precharged to a specified precharge voltage level and the precharge voltage is less than a threshold voltage of the first diode and second diode.

    Abstract translation: 存储单元包括磁性隧道结数据单元电耦合到位线和源极线。 磁隧道结数据单元被配置为通过使写入电流通过磁性隧道结数据单元而在高电阻状态和低电阻状态之间切换。 第一二极管电磁性地在磁性隧道结数据单元和源极线之间，第二个二极管电气地在磁性隧道结数据单元和源极线之间。 第一二极管和第二二极管并联电连接并具有相反的正向偏压方向。 存储器单元被配置为预充电到指定的预充电电压电平，并且预充电电压小于第一二极管和第二二极管的阈值电压。

    Non-volatile memory cell with resistive sense element block erase and uni-directional write
    12.
    发明授权
    Non-volatile memory cell with resistive sense element block erase and uni-directional write 有权
    具有电阻感测元件块擦除和单向写入的非易失性存储单元

    公开(公告)号：US08213259B2

    公开(公告)日：2012-07-03

    申请号：US12903011

    申请日：2010-10-12

    Applicant: Daniel S. Reed ,  Yong Lu ,  Andrew John Carter ,  Hai Li

    Inventor： Daniel S. Reed ,  Yong Lu ,  Andrew John Carter ,  Hai Li

    IPC: G11C7/12 ,  G11C8/08 ,  G11C11/21 ,  G11C11/02 ,  G11C7/22

    CPC classification number: G11C13/0097 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/003 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/76

    Abstract: A non-volatile memory cell and associated method of use. In accordance with some embodiments, the memory cell includes a transistor comprising source and drain regions spanned by a gate region, and a resistive sense element (RSE) connected to the drain region of the transistor. The RSE is programmed to a first resistance by flowing a first write current through the RSE and then through the drain and source regions of the transistor. The RSE is programmed to a second resistance by flowing a second write current through the drain region and then through the RSE, the second write current bypassing the source region.

    Abstract translation: 非易失性存储单元及相关联的使用方法。 根据一些实施例，存储器单元包括晶体管，其包括由栅极区域跨越的源极和漏极区域，以及连接到晶体管的漏极区域的电阻感测元件（RSE）。 通过使第一写入电流流过RSE然后通过晶体管的漏极和源极区域将RSE编程为第一电阻。 通过使第二写入电流流经漏极区域，然后通过RSE，将第二电阻编程为第二电阻，第二写入电流绕过源极区域。

    Bit line charge accumulation sensing for resistive changing memory
    13.
    发明授权
    Bit line charge accumulation sensing for resistive changing memory 有权
    电阻变化存储器的位线电荷累积检测

    公开(公告)号：US08203869B2

    公开(公告)日：2012-06-19

    申请号：US12326184

    申请日：2008-12-02

    Applicant: Chulmin Jung ,  Yong Lu ,  Kang Yong Kim ,  Young Pil Kim

    Inventor： Chulmin Jung ,  Yong Lu ,  Kang Yong Kim ,  Young Pil Kim

    IPC: G11C11/00

    CPC classification number: G11C7/14 ,  G11C7/02 ,  G11C7/04 ,  G11C7/062 ,  G11C11/1673

    Abstract: A memory array includes a plurality of magneto-resistive changing memory cells. Each resistive changing memory cell is electrically between a source line and a bit line and a transistor electrically between the resistive changing memory cell and the bit line. The transistor has a gate electrically between a source region and a drain region and the source region being electrically between the magneto-resistive changing memory cell and the gate. A word line is electrically coupled to the gate. A bit line charge accumulation sensing for magneto-resistive changing memory is also disclosed.

    Abstract translation: 存储器阵列包括多个磁阻改变存储单元。 每个电阻变化存储单元在电源线和位线之间电连接，并且电阻在电阻变化存储单元和位线之间。 晶体管在源极区域和漏极区域之间具有电门，并且源极区域在电磁变化存储单元和栅极之间电连接。 字线电耦合到门。 还公开了用于磁阻改变存储器的位线电荷累积感测。

    Spin-transfer torque memory self-reference read method
    14.
    发明授权
    Spin-transfer torque memory self-reference read method 有权
    自旋转矩记忆自参考读取方式

    公开(公告)号：US08194444B2

    公开(公告)日：2012-06-05

    申请号：US12968441

    申请日：2010-12-15

    Applicant: Yuankai Zheng ,  Yiran Chen ,  Xiaobin Wang ,  Zheng Gao ,  Dimitar V. Dimitrov ,  Wenzhong Zhu ,  Yong Lu

    Inventor： Yuankai Zheng ,  Yiran Chen ,  Xiaobin Wang ,  Zheng Gao ,  Dimitar V. Dimitrov ,  Wenzhong Zhu ,  Yong Lu

    IPC: G11C11/14 ,  G11C11/00 ,  G11C7/00 ,  G11C7/02

    CPC classification number: G11C11/1673

    Abstract: Self-reference reading a magnetic tunnel junction data cell methods are disclosed. An illustrative method includes applying a read voltage across a magnetic tunnel junction data cell and forming a read current. The magnetic tunnel junction data cell has a first resistance state. The read voltage is sufficient to switch the magnetic tunnel junction data cell resistance. The method includes detecting the read current and determining if the read current remains constant during the applying step. If the read current remains constant during the applying step, then the first resistance state of the magnetic tunnel junction data cell is the resistance state that the read voltage was sufficient to switch the magnetic tunnel junction data cell to.

    Abstract translation: 公开了自参考读取磁隧道结数据单元方法。 一种说明性方法包括在磁性隧道结数据单元上施加读取电压并形成读取电流。 磁性隧道结数据单元具有第一电阻状态。 读取电压足以切换磁性隧道结数据单元电阻。 该方法包括检测读取电流并确定在施加步骤期间读取电流是否保持恒定。 如果在施加步骤期间读取电流保持恒定，则磁性隧道结数据单元的第一电阻状态是读取电压足以将磁性隧道结数据单元切换到的电阻状态。

    Aggregation of product data provided from external sources for presentation on an E-commerce website
    17.
    发明授权
    Aggregation of product data provided from external sources for presentation on an E-commerce website 有权
    汇总从外部来源提供的产品数据，以呈现在电子商务网站上

    公开(公告)号：US08086496B2

    公开(公告)日：2011-12-27

    申请号：US12025791

    申请日：2008-02-05

    Applicant: Yong Lu ,  Trevin Chow ,  Herman John Man ,  Derek Lynn Jamison ,  Mark Wong

    Inventor： Yong Lu ,  Trevin Chow ,  Herman John Man ,  Derek Lynn Jamison ,  Mark Wong

    IPC: G06Q30/00

    CPC classification number: G06Q30/0603 ,  G06Q30/0601

    Abstract: Aggregation of product data provided from external sources of product data for presentation on an e-commerce website. A set of product data related to a product that is offered for sale in e-commerce is accessed and subjected to an aggregation process. The set of product data is mapped for aggregation with other sets of product data based on an existing mapping or on an absence of an existing mapping. Access is provided to an aggregated set of product data that includes the set of product data that is mapped for aggregation with other sets of product data, for presentation on an e-commerce website.

    Abstract translation: 从产品数据的外部来源提供的产品数据汇总在电子商务网站上进行汇总。 与在电子商务中出售的产品相关的一组产品数据被访问并进行聚合处理。 基于现有映射或缺少现有映射，将该组产品数据映射为与其他产品数据集合进行聚合。 将访问权提供给一组聚合的产品数据，其中包括一组产品数据，该产品数据映射为与其他产品数据集合进行聚合，以供在电子商务网站上呈现。

    Variable write and read methods for resistive random access memory
    18.
    发明授权
    Variable write and read methods for resistive random access memory 失效
    电阻随机存取存储器的可变写和读方法

    公开(公告)号：US08054675B2

    公开(公告)日：2011-11-08

    申请号：US13028246

    申请日：2011-02-16

    Applicant: Haiwen Xi ,  Hongyue Liu ,  Xiaobin Wang ,  Yong Lu ,  Yiran Chen ,  Yuankai Zheng ,  Dimitar V. Dimitrov ,  Dexin Wang ,  Hai Li

    Inventor： Haiwen Xi ,  Hongyue Liu ,  Xiaobin Wang ,  Yong Lu ,  Yiran Chen ,  Yuankai Zheng ,  Dimitar V. Dimitrov ,  Dexin Wang ,  Hai Li

    IPC: G11C11/00 ,  G11C11/14 ,  G11C11/15

    CPC classification number: G11C11/16 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0057

    Abstract: Variable write and read methods for resistance random access memory (RRAM) are disclosed. The methods include initializing a write sequence and verifying the resistance state of the RRAM cell. If a write pulse is needed, then two or more write pulses are applied through the RRAM cell to write the desired data state to the RRAM cell. Each subsequent write pulse has substantially the same or greater write pulse duration. Subsequent write pulses are applied to the RRAM cell until the RRAM cell is in the desired data state or until a predetermined number of write pulses have been applied to the RRAM cell. A read method is also disclosed where subsequent read pulses are applied through the RRAM cell until the read is successful or until a predetermined number of read pulses have been applied to the RRAM cell.

    Abstract translation: 公开了用于电阻随机存取存储器（RRAM）的可变写和读方法。 这些方法包括初始化写入序列并验证RRAM单元的电阻状态。 如果需要写入脉冲，则通过RRAM单元施加两个或更多写入脉冲，以将期望的数据状态写入RRAM单元。 每个后续写入脉冲具有基本上相同或更大的写入脉冲持续时间。 随后的写入脉冲被施加到RRAM单元，直到RRAM单元处于期望的数据状态，或直到预定数量的写入脉冲已经被施加到RRAM单元为止。 还公开了一种读取方法，其中随后的读取脉冲通过RRAM单元被施加，直到读取成功或直到预定数量的读取脉冲已经被应用于RRAM单元为止。

    Mirrored-gate cell for non-volatile memory
    19.
    发明授权
    Mirrored-gate cell for non-volatile memory 失效
    用于非易失性存储器的镜像门单元

    公开(公告)号：US08053749B2

    公开(公告)日：2011-11-08

    申请号：US12389817

    申请日：2009-02-20

    Applicant: Roger Glenn Rolbiecki ,  Andrew Carter ,  Yong Lu

    Inventor： Roger Glenn Rolbiecki ,  Andrew Carter ,  Yong Lu

    IPC: H01L47/00

    CPC classification number: H01L27/0207 ,  H01L27/105 ,  H01L27/11803 ,  H01L27/228 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233

    Abstract: A memory comprising at least one memory cell operationally connected to a bit line, a source line and a word line. The memory cell comprises a substrate having a first source contact, a second source contact, and a bit contact between the first source contact and the second source contact, a first transistor gate electrically connecting the first source contact and the bit contact and a second transistor gate electrically connecting the bit contact and the second source contact. The word line electrically connects the first transistor gate to the second transistor gate.

    Abstract translation: 一种存储器，包括至少一个可操作地连接到位线，源极线和字线的存储单元。 存储单元包括具有第一源极触点，第二源极触点和第一源极触点和第二源极触点之间的位接触的基板，电连接第一源极触点和位触点的第一晶体管栅极和第二晶体管 栅极电连接位触点和第二源触点。 字线将第一晶体管栅极电连接到第二晶体管栅极。

    Floating source line architecture for non-volatile memory
    20.
    发明授权
    Floating source line architecture for non-volatile memory 有权
    用于非易失性存储器的浮动源线架构

    公开(公告)号：US08004872B2

    公开(公告)日：2011-08-23

    申请号：US12272507

    申请日：2008-11-17

    Applicant: Chulmin Jung ,  Yong Lu ,  Harry Hongyue Liu

    Inventor： Chulmin Jung ,  Yong Lu ,  Harry Hongyue Liu

    IPC: G11C11/10

    CPC classification number: G11C13/0002 ,  G11C7/12 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0069

    Abstract: A method and apparatus for writing data to a non-volatile memory cell, such as an RRAM memory cell. In some embodiments, a semiconductor array of non-volatile memory cells comprises a resistive sense element (RSE) and a switching device. A RSE of a plurality of memory cells is connected to a bit line while the switching device of a plurality of memory cells is connected to a word line and operated to select a memory cell. A source line is connected to the switching device and connects a series of memory cells together. Further, a driver circuit is connected to the bit line and writes a selected RSE of a selected source line to a selected resistive state by passing a write current along a write current path that passes through the selected RSE and through at least a portion of the remaining RSE connected to the selected source line.

    Abstract translation: 一种将数据写入诸如RRAM存储单元的非易失性存储单元的方法和装置。 在一些实施例中，非易失性存储单元的半导体阵列包括电阻感测元件（RSE）和开关器件。 多个存储单元的RSE连接到位线，而多个存储单元的开关器件连接到字线并被操作以选择存储器单元。 源极线连接到开关器件，并将一系列存储器单元连接在一起。 此外，驱动器电路连接到位线，并且通过使写入电流沿着通过所选择的RSE的写入电流路径并且通过至少一部分所述选择的RSE而将所选择的源极线的选定RSE写入所选择的电阻状态 剩余的RSE连接到所选择的源线。

Patent Agency Ranking