公开(公告)号：US08090823B2

公开(公告)日：2012-01-03

申请号：US12259942

申请日：2008-10-28

申请人： James Stephen Fields, Jr. ,  Paul Frank Lecocq ,  Brian Chan Monwai ,  Thomas Pflueger ,  Kevin Franklin Reick ,  Timothy M. Skergan ,  Scott Barnett Swaney

发明人： James Stephen Fields, Jr. ,  Paul Frank Lecocq ,  Brian Chan Monwai ,  Thomas Pflueger ,  Kevin Franklin Reick ,  Timothy M. Skergan ,  Scott Barnett Swaney

IPC分类号： G06F15/173 ,  G06F15/167

CPC分类号： G06F15/161

摘要： Illustrative embodiments disclose a data processing system providing low-level hardware access to in-band and out-of-band firmware. The data processing system includes a plurality of chips that includes at least one processor chip and a plurality of support chips. At least one processor chip includes a field replaceable unit support interface master that uses a field replaceable unit support interface serial transmission protocol to communicate with the plurality of support chips. Each one of the plurality of support chips includes a field replaceable unit support interface slave in, with ones of the plurality of chips that include a processor also include the field replaceable unit support interface master, and ones of the plurality of chips that do not include the processor include only the field replaceable unit support interface slave. Only the field replaceable unit support interface master possesses conversion logic.

摘要翻译： 说明性实施例公开了提供对带内和带外固件的低级硬件访问的数据处理系统。 数据处理系统包括多个芯片，其包括至少一个处理器芯片和多个支持芯片。 至少一个处理器芯片包括使用现场可更换单元支持接口串行传输协议与多个支持芯片进行通信的现场可更换单元支持接口主机。 多个支持芯片中的每一个包括现场可更换单元支持接口从机，其中包括处理器的多个芯片中的一个包括现场可更换单元支持接口主机，以及不包括的多个芯片中的一个 处理器仅包括现场可更换单元支持接口从站。 只有现场可更换单元支持接口主机具有转换逻辑。

公开(公告)号：US6006311A

公开(公告)日：1999-12-21

申请号：US839559

申请日：1997-04-14

申请人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Jerry Don Lewis ,  Timothy M. Skergan

发明人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Jerry Don Lewis ,  Timothy M. Skergan

IPC分类号： G06F13/00 ,  G11C29/00

CPC分类号： G11C29/88 ,  G06F12/126 ,  G11C29/76 ,  G06F2212/1032

摘要： A method of dynamically avoiding defective cache lines in a cache used by a processor of a computer system is disclosed. A repair mask is used, having an array of bit fields each corresponding to a cache lines in the cache, and certain bit fields in the repair mask array are initially set to indicate that a group of corresponding cache lines are defective. Thereafter the repair mask is updated by setting additional bit fields in the repair mask array to indicate that an additional group of corresponding cache lines are defective. Access to all defective cache lines is prevented based on the corresponding bit fields in the repair mask array. The initial setting of certain bit fields can take place at fabrication of the cache chip in response to testing of the cache lines. Additionally, the repair mask may be updated each time the computer system is booted in response to testing by the boot procedure. The repair mask may also be updated real-time during program execution in response to detection of an error associated with a particular cache line. Updating in real-time can be accomplished by counting a cumulative number of errors associated with a cache line, and then identifying the cache line as being defective only after a certain number of cumulative errors has occurred.

摘要翻译： 公开了一种动态地避免由计算机系统的处理器使用的高速缓存中的有缺陷的高速缓存行的方法。 使用具有每个对应于高速缓存中的高速缓存行的位字段阵列的修复掩码，并且初始设置修复掩码阵列中的某些位字段以指示一组对应的高速缓存行有缺陷。 此后，通过在修复掩码阵列中设置附加位字段来指示修复掩码被更新以指示附加的一组对应的高速缓存行是有缺陷的。 基于修复掩码阵列中的相应位字段来防止对所有有缺陷的高速缓存行的访问。 响应于高速缓存行的测试，可以在制造高速缓存芯片时进行某些位字段的初始设置。 此外，每当计算机系统引导时响应于引导过程的测试，可以更新修复掩码。 响应于检测到与特定高速缓存行相关联的错误，修复掩码也可以在程序执行期间被实时更新。 可以通过计数与高速缓存行相关联的错误的累积数量，然后将高速缓存行识别为在发生一定数量的累积错误之后的缺陷来实现。

公开(公告)号：US07916722B2

公开(公告)日：2011-03-29

申请号：US12139631

申请日：2008-06-16

申请人： James Stephen Fields, Jr. ,  Paul Frank Lecocq ,  Brian Chan Monwai ,  Thomas Pflueger ,  Kevin Franklin Reick ,  Timothy M. Skergan ,  Scott Barnett Swaney

发明人： James Stephen Fields, Jr. ,  Paul Frank Lecocq ,  Brian Chan Monwai ,  Thomas Pflueger ,  Kevin Franklin Reick ,  Timothy M. Skergan ,  Scott Barnett Swaney

IPC分类号： H04L12/28 ,  H04L12/56 ,  H04L12/66 ,  G06F3/00 ,  G06F12/00

CPC分类号： G06F15/7842

摘要： A method and apparatus are provided for a support interface for memory-mapped resources. A support processor sends a sequence of commands over and FSI interface to a memory-mapped support interface on a processor chip. The memory-mapped support interface updates memory, memory-mapped registers or memory-mapped resources. The interface uses fabric packet generation logic to generate a single command packet in a protocol for the coherency fabric which consists of an address, command and/or data. Fabric commands are converted to FSI protocol and forwarded to attached support chips to access the memory-mapped resource, and responses from the support chips are converted back to fabric response packets. Fabric snoop logic monitors the coherency fabric and decodes responses for packets previously sent by fabric packet generation logic. The fabric snoop logic updates status register and/or writes response data to a read data register. The system also reports any errors that are encountered.

摘要翻译： 提供了一种用于存储器映射资源的支持接口的方法和装置。 支持处理器将一系列命令和FSI接口发送到处理器芯片上的存储器映射支持接口。 内存映射支持接口更新内存，内存映射寄存器或内存映射资源。 该接口使用结构数据包生成逻辑在由地址，命令和/或数据组成的一致性结构的协议中生成单个命令分组。 结构命令转换为FSI协议，并转发到附加的支持芯片以访问存储器映射的资源，并且来自支持芯片的响应被转换回到结构响应分组。 Fabric监听逻辑监视一致性结构，并解码先前由Fabric数据包生成逻辑发送的数据包的响应。 织物窥探逻辑更新状态寄存器和/或将响应数据写入读取数据寄存器。 系统还报告遇到的任何错误。

公开(公告)号：US06550020B1

公开(公告)日：2003-04-15

申请号：US09483260

申请日：2000-01-10

申请人： Michael Stephen Floyd ,  Kevin F. Reick ,  Timothy M. Skergan

发明人： Michael Stephen Floyd ,  Kevin F. Reick ,  Timothy M. Skergan

IPC分类号： G06F1100

CPC分类号： G06F11/2028 ,  G06F11/1417 ,  G06F11/2035

摘要： A data processing system has at least one integrated circuit containing a central processing unit (CPU) that includes at least first and second processing cores. The integrated circuit also includes input facilities that receive control input specifying which of the processing cores is to be utilized. In addition, the integrated circuit includes configuration logic that decodes the control input and, in response, selectively controls reception of input signals and transmission of output signals of one or more of the processing cores in accordance with the control input. In an illustrative embodiment, the configuration logic is partial-good logic that configures the integrated circuit to utilize the second processing core, in lieu of a defective or inactive first processing core, as a virtual first processing core.

摘要翻译： 数据处理系统具有至少一个包含至少包括第一和第二处理核心的中央处理单元（CPU）的集成电路。 该集成电路还包括接收控制输入的输入设备，该控制输入指定要使用哪个处理核心。 此外，集成电路包括对控制输入进行解码的配置逻辑，并且作为响应，根据控制输入选择性地控制输入信号的接收和一个或多个处理核的输出信号的传输。 在说明性实施例中，配置逻辑是部分良好的逻辑，其将集成电路配置为利用第二处理核，以代替有缺陷或不活动的第一处理核作为虚拟第一处理核。

公开(公告)号：US6085288A

公开(公告)日：2000-07-04

申请号：US839556

申请日：1997-04-14

申请人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Jerry Don Lewis ,  Timothy M. Skergan

发明人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Jerry Don Lewis ,  Timothy M. Skergan

IPC分类号： G06F12/16 ,  G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0831

摘要： A method of storing values in a cache used by a processor of a computer system, the cache having two or more cache directories. An address tag associated with the memory block is written into a first cache directory during an initial processor cycle, the address tag is written into a second cache directory during the next or subsequent processor cycle. Another address tag associated with a different memory block may be read from the second cache directory during the initial processor cycle. Additionally, another address tag associated with yet a different memory block may be read from the first cache directory during the subsequent processor cycle. A write operation for the address tag may be placed into a write queue of the first cache directory, prior to writing the address tag into the first cache directory, and the same write operation may be placed into a write queue of the second cache directory, prior to said step of writing the address tag into the second cache directory; the write queue of the second cache directory executes its contents independently of the write queue of the first cache directory. This staggered writing ability imparts greater flexibility in carrying out write operations for a cache having multiple directories, thereby increasing performance.

摘要翻译： 一种在计算机系统的处理器使用的高速缓存中存储值的方法，所述高速缓存具有两个或多个高速缓存目录。 在初始处理器周期期间，与存储器块相关联的地址标签被写入第一高速缓存目录中，在下一个或后续处理器周期期间将地址标签写入第二高速缓存目录。 可以在初始处理器周期期间从第二高速缓存目录读取与不同存储器块相关联的另一地址标签。 此外，在随后的处理器周期期间，可以从第一高速缓存目录读取与另一个存储器块相关联的另一地址标签。 在将地址标签写入第一高速缓存目录之前，可以将地址标签的写入操作放入第一高速缓存目录的写入队列中，并且可以将相同的写入操作放入第二高速缓存目录的写入队列中， 在将所述地址标签写入所述第二高速缓存目录之前的所述步骤之前; 第二高速缓存目录的写入队列独立于第一高速缓存目录的写入队列来执行其内容。 这种交错的写入能力为对具有多个目录的高速缓存执行写入操作赋予更大的灵活性，从而提高性能。

公开(公告)号：US08365006B2

公开(公告)日：2013-01-29

申请号：US12836103

申请日：2010-07-14

申请人： Steven M. Douskey ,  Thomas Pflueger ,  Edward M. Seymour ,  Timothy M. Skergan

发明人： Steven M. Douskey ,  Thomas Pflueger ,  Edward M. Seymour ,  Timothy M. Skergan

IPC分类号： G06F1/10

CPC分类号： G06F1/04 ,  G06F21/70

摘要： For disabling a first function in an information handling system, a dynamic signal is disabled. The first function is inoperable in response to the dynamic signal being disabled. At least a second function in the information handling system is operable irrespective of whether the dynamic signal is disabled.

摘要翻译： 为了禁用信息处理系统中的第一个功能，禁用动态信号。 响应于动态信号被禁用，第一个功能是无法操作的。 无论动态信号是否被禁用，信息处理系统中的至少第二功能是可操作的。

公开(公告)号：US20120151288A1

公开(公告)日：2012-06-14

申请号：US12963246

申请日：2010-12-08

申请人： William B. Maloney ,  Timothy M. Skergan

发明人： William B. Maloney ,  Timothy M. Skergan

IPC分类号： G06F11/26

CPC分类号： G01R31/318583 ,  G06F17/505 ,  G06F2217/14

摘要： Mechanisms are provided for creating shift register definition from high-level model using high-level model simulation. The mechanisms initialize all potential scan chain latches, identify the latches in a given scan chain, and separate the scan chain latches into chunks. For each chunk, the mechanisms identify the latches within the chunk that change at each shift. The mechanisms isolate the scan path latch when divergence occurs.

摘要翻译： 提供了使用高级模型模拟从高级模型创建移位寄存器定义的机制。 机制初始化所有潜在的扫描链锁存器，识别给定扫描链中的锁存器，并将扫描链锁存器分成多个块。 对于每个块，这些机制识别块中每个位移处的锁存器。 当出现发散时，机制将隔离扫描路径锁存器。

公开(公告)号：US20090055563A1

公开(公告)日：2009-02-26

申请号：US12259942

申请日：2008-10-28

申请人： James Stephen Fields, JR. ,  Paul Frank Lecocq ,  Brian Chan Monwai ,  Thomas Pflueger ,  Kevin Franklin Reick ,  Timothy M. Skergan ,  Scott Barnett Swaney

发明人： James Stephen Fields, JR. ,  Paul Frank Lecocq ,  Brian Chan Monwai ,  Thomas Pflueger ,  Kevin Franklin Reick ,  Timothy M. Skergan ,  Scott Barnett Swaney

IPC分类号： G06F13/42

CPC分类号： G06F15/161

摘要： In-band firmware executes instructions which cause commands to be sent on a coherency fabric. Fabric snoop logic monitors the coherency fabric for command packets that target a resource in one of the support chips attached via an FSI link. Conversion logic converts the information from the fabric packet into an FSI protocol. An FSI command is transmitted via the FSI transmit link to an FSI slave of the intended support chip. An FSI receive link receives response data from the FSI slave of the intended support chip. Conversion logic converts the information from the support chip received via the FSI receive link into the fabric protocol. Response packet generation logic generates the fabric response packet and returns it on the coherency fabric. An identical FSI link between a support processor and support chips allows direct access to the same resources on the support chips by out-of-band firmware.

摘要翻译： 带内固件执行指令，使指令在一致性结构上发送。 Fabric Snoop逻辑监视针对通过FSI链接附加的支持芯片之一的资源的命令包的一致性结构。 转换逻辑将信息从Fabric数据包转换为FSI协议。 FSI命令通过FSI传输链路发送到预期支持芯片的FSI从站。 FSI接收链路从预期的支持芯片的FSI从站接收响应数据。 转换逻辑将从通过FSI接收链路接收的支持芯片的信息转换为结构协议。 响应分组生成逻辑生成结构响应分组并将其返回到一致性结构上。 支持处理器和支持芯片之间的相同FSI链路允许通过带外固件直接访问支持芯片上的相同资源。

公开(公告)号：US20080247415A1

公开(公告)日：2008-10-09

申请号：US12139631

申请日：2008-06-16

申请人： James Stephen Fields ,  Paul Frank Lecocq ,  Brian Chan Monwai ,  Thomas Pflueger ,  Kevin Franklin Reick ,  Timothy M. Skergan ,  Scott Barnett Swaney

发明人： James Stephen Fields ,  Paul Frank Lecocq ,  Brian Chan Monwai ,  Thomas Pflueger ,  Kevin Franklin Reick ,  Timothy M. Skergan ,  Scott Barnett Swaney

IPC分类号： H04L12/66

CPC分类号： G06F15/7842

摘要： A method and apparatus are provided for a support interface for memory-mapped resources. A support processor sends a sequence of commands over and FSI interface to a memory-mapped support interface on a processor chip. The memory-mapped support interface updates memory, memory-mapped registers or memory-mapped resources. The interface uses fabric packet generation logic to generate a single command packet in a protocol for the coherency fabric which consists of an address, command and/or data. Fabric commands are converted to FSI protocol and forwarded to attached support chips to access the memory-mapped resource, and responses from the support chips are converted back to fabric response packets. Fabric snoop logic monitors the coherency fabric and decodes responses for packets previously sent by fabric packet generation logic. The fabric snoop logic updates status register and/or writes response data to a read data register. The system also reports any errors that are encountered.

摘要翻译： 提供了一种用于存储器映射资源的支持接口的方法和装置。 支持处理器将一系列命令和FSI接口发送到处理器芯片上的存储器映射支持接口。 内存映射支持接口更新内存，内存映射寄存器或内存映射资源。 该接口使用结构数据包生成逻辑在由地址，命令和/或数据组成的一致性结构的协议中生成单个命令分组。 结构命令转换为FSI协议，并转发到附加的支持芯片以访问存储器映射的资源，并且来自支持芯片的响应被转换回到结构响应分组。 Fabric监听逻辑监视一致性结构，并解码先前由Fabric数据包生成逻辑发送的数据包的响应。 织物窥探逻辑更新状态寄存器和/或将响应数据写入读取数据寄存器。 系统还报告遇到的任何错误。

公开(公告)号：US20080224714A1

公开(公告)日：2008-09-18

申请号：US11685226

申请日：2007-03-13

申请人： Tanit Virutchapunt ,  Sungjun Chun ,  Timothy M. Skergan ,  Roger D. Weekly

发明人： Tanit Virutchapunt ,  Sungjun Chun ,  Timothy M. Skergan ,  Roger D. Weekly

IPC分类号： G01R27/02

CPC分类号： G01R31/31922 ,  G01R27/02 ,  G01R31/31937

摘要： A system and method of integrated circuit control for in situ impedance measurement including a system with a plurality of functional partitions in a clocked logic type integrated circuit, the functional partitions having a communication controller and a modulation gate, the modulation gate receiving a clock signal and a modulation signal and generating a modulated clock signal for the functional partition; at least one of the communication controllers receiving an in-band signal and selectively communicating the in-band signal to the other communication controllers; and at least one of the functional partitions having a modulator, the modulator receiving the clock signal and a modulation control signal and generating the modulation signal.

摘要翻译： 一种用于原位阻抗测量的集成电路控制的系统和方法，包括在时钟逻辑型集成电路中具有多个功能分区的系统，功能分区具有通信控制器和调制门，调制门接收时钟信号， 调制信号并产生用于功能分区的调制时钟信号; 所述通信控制器中的至少一个接收带内信号并选择性地将所述带内信号传送到所述其他通信控制器; 并且功能分区中的至少一个具有调制器，调制器接收时钟信号和调制控制信号并产生调制信号。