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公开(公告)号：US20190101973A1
公开(公告)日：2019-04-04
申请号：US15721109
申请日：2017-09-29
Applicant: Advanced Micro Devices, Inc.
Inventor： Alexander Fuad Ashkar , Angel E. Socarras , Rex Eldon McCrary
IPC: G06F1/32
Abstract: Systems, apparatuses, and methods for dynamically adjusting the power consumption of prefetch engines are disclosed. In one embodiment, a processor includes one or more prefetch engines, a draw completion engine, and a queue in between the one or more prefetch engines and the draw completion engine. If the number of packets stored in the queue is greater than a high watermark, then the processor reduces the power state of the prefetch engine(s). By decreasing the power state of the prefetch engine(s), power consumption is reduced. Additionally, this power consumption reduction is achieved without affecting performance, since the queue has a high occupancy and the draw completion engine can continue to read packets out of the queue. If the number of packets stored in the queue is less than a low watermark, then the processor increases the power state of the prefetch engine(s).
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公开(公告)号：US11948223B2
公开(公告)日：2024-04-02
申请号：US17862096
申请日：2022-07-11
Applicant: Advanced Micro Devices, Inc.
Inventor： Michael J. Mantor , Jeffrey T. Brady , Angel E. Socarras
CPC classification number: G06T1/20 , G06T1/60 , G09G5/363 , G09G2360/06
Abstract: Methods and systems are described. A system includes a redundant shader pipe array that performs rendering calculations on data provided thereto and a shader pipe array that includes a plurality of shader pipes, each of which performs rendering calculations on data provided thereto. The system also includes a circuit that identifies a defective shader pipe of the plurality of shader pipes in the shader pipe array. In response to identifying the defective shader pipe, the circuit generates a signal. The system also includes a redundant shader switch. The redundant shader switch receives the generated signal, and, in response to receiving the generated signal, transfers the data for the defective shader pipe to the redundant shader pipe array.
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公开(公告)号：US11386520B2
公开(公告)日：2022-07-12
申请号：US17113827
申请日：2020-12-07
Applicant: Advanced Micro Devices, Inc.
Inventor： Michael J. Mantor , Jeffrey T. Brady , Angel E. Socarras
Abstract: Methods and systems are described. A system includes a redundant shader pipe array that performs rendering calculations on data provided thereto and a shader pipe array that includes a plurality of shader pipes, each of which performs rendering calculations on data provided thereto. The system also includes a circuit that identifies a defective shader pipe of the plurality of shader pipes in the shader pipe array. In response to identifying the defective shader pipe, the circuit generates a signal. The system also includes a redundant shader switch. The redundant shader switch receives the generated signal, and, in response to receiving the generated signal, transfers the data for the defective shader pipe to the redundant shader pipe array.
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公开(公告)号：US10955901B2
公开(公告)日：2021-03-23
申请号：US15721109
申请日：2017-09-29
Applicant: Advanced Micro Devices, Inc.
Inventor： Alexander Fuad Ashkar , Angel E. Socarras , Rex Eldon McCrary
IPC: G06F1/00 , G06F1/3234 , G06F1/324 , G06F1/3296 , G06F1/3287 , G06F1/3203
Abstract: Systems, apparatuses, and methods for dynamically adjusting the power consumption of prefetch engines are disclosed. In one embodiment, a processor includes one or more prefetch engines, a draw completion engine, and a queue in between the one or more prefetch engines and the draw completion engine. If the number of packets stored in the queue is greater than a high watermark, then the processor reduces the power state of the prefetch engine(s). By decreasing the power state of the prefetch engine(s), power consumption is reduced. Additionally, this power consumption reduction is achieved without affecting performance, since the queue has a high occupancy and the draw completion engine can continue to read packets out of the queue. If the number of packets stored in the queue is less than a low watermark, then the processor increases the power state of the prefetch engine(s).
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15.发明授权公开(公告)号：US10311626B2
公开(公告)日：2019-06-04
申请号：US15297611
申请日：2016-10-19
Applicant: Advanced Micro Devices, Inc.
Inventor： Rashad Oreifej , Angel E. Socarras , Mark Russell Anderson , Randy Wayne Ramsey
Abstract: A GPU filters graphics workloads to identify candidates for profiling. In response to receiving a graphics workload for the first time, the GPU determines if the graphics workload would require the GPU shaders to use fewer resources than would be spent profiling and determining a resource allocation for subsequent receipts of the same or a similar graphics workload. The GPU can further determine if the shaders are processing more than one graphics workload at the same time, such that the performance characteristics of each individual graphics workload cannot be effectively isolated. The GPU then profiles and stores resource allocations for a plurality of shaders for processing the filtered graphics workloads, and applies those stored resource allocations when the same or a similar graphics workload is received subsequently by the GPU.
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Patent Agency Ranking
16.发明申请公开(公告)号：US20180108166A1
公开(公告)日：2018-04-19
申请号：US15297611
申请日：2016-10-19
Applicant: Advanced Micro Devices, Inc.
Inventor： Rashad Oreifej , Angel E. Socarras , Mark Russell Anderson , Randy Wayne Ramsey
CPC classification number: G06T15/005 , G06F9/38
Abstract: A GPU filters graphics workloads to identify candidates for profiling. In response to receiving a graphics workload for the first time, the GPU determines if the graphics workload would require the GPU shaders to use fewer resources than would be spent profiling and determining a resource allocation for subsequent receipts of the same or a similar graphics workload. The GPU can further determine if the shaders are processing more than one graphics workload at the same time, such that the performance characteristics of each individual graphics workload cannot be effectively isolated. The GPU then profiles and stores resource allocations for a plurality of shaders for processing the filtered graphics workloads, and applies those stored resource allocations when the same or a similar graphics workload is received subsequently by the GPU.
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公开(公告)号：US09367891B2
公开(公告)日：2016-06-14
申请号：US14808113
申请日：2015-07-24
Applicant: Advanced Micro Devices, Inc.
Inventor： Michael J. Mantor , Jeffrey T. Brady , Angel E. Socarras
CPC classification number: G06T1/20 , G06T1/60 , G09G5/363 , G09G2360/06
Abstract: Methods, systems and non-transitory computer readable media are described. A system includes a shader pipe array, a redundant shader pipe array, a sequencer and a redundant shader switch. The shader pipe array includes multiple shader pipes, each of which perform rendering calculations on data provided thereto. The redundant shader pipe array also performs rendering calculations on data provided thereto. The sequencer identifies at least one defective shader pipe in the shader pipe array, and, in response, generates a signal. The redundant shader switch receives the generated signal, and, in response, transfers the data destined for each shader pipe identified as being defective independently to the redundant shader pipe array.
Abstract translation: 描述了方法，系统和非暂时性计算机可读介质。 系统包括着色器管道阵列，冗余着色器管道阵列，定序器和冗余着色器开关。 着色器管道阵列包括多个着色器管道，每个管道对其提供的数据执行渲染计算。 冗余着色器管道阵列还对提供给它的数据执行渲染计算。 定序器在着色器管道阵列中识别至少一个有缺陷的着色器管道，并作为响应生成信号。 冗余着色器开关接收所生成的信号，并作为响应，将指定为每个着色器管道的数据独立地传输到冗余着色器管道阵列。
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公开(公告)号：US20220343456A1
公开(公告)日：2022-10-27
申请号：US17862096
申请日：2022-07-11
Applicant: Advanced Micro Devices, Inc.
Inventor： Michael J. Mantor , Jeffrey T. Brady , Angel E. Socarras
Abstract: Methods and systems are described. A system includes a redundant shader pipe array that performs rendering calculations on data provided thereto and a shader pipe array that includes a plurality of shader pipes, each of which performs rendering calculations on data provided thereto. The system also includes a circuit that identifies a defective shader pipe of the plurality of shader pipes in the shader pipe array. In response to identifying the defective shader pipe, the circuit generates a signal. The system also includes a redundant shader switch. The redundant shader switch receives the generated signal, and, in response to receiving the generated signal, transfers the data for the defective shader pipe to the redundant shader pipe array.
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公开(公告)号：US10198358B2
公开(公告)日：2019-02-05
申请号：US14243050
申请日：2014-04-02
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Angel E. Socarras , Kostantinos Danny Christidis , Curtis Alan Gilgan , Alexander Fuad Ashkar
IPC: G06F12/0875 , G06F11/22 , G06F11/30 , G06F11/273
Abstract: Apparatuses, computer readable mediums, and methods of processor unit testing using cache resident testing are disclosed. The method may include loading a test program in a cache on a chip comprising one or more processor units. The method may include the one or more processor units executing the test program to generate one or more results. The method may include redirecting a first memory reference to the cache, wherein the first memory reference is generated during the execution of the test program. The method may include determining whether the one or more generated results match one or more test results. The method may include redirecting a memory request to a memory location resident in the cache if the memory request includes a memory location not resident in the cache. The method may include redirecting a memory request to the cache if the memory request is not directed to the cache.
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公开(公告)号：US10096081B2
公开(公告)日：2018-10-09
申请号：US15270679
申请日：2016-09-20
Applicant: Advanced Micro Devices, Inc.
Inventor： Alexander Fuad Ashkar , Harry J. Wise , Rex Eldon McCrary , Angel E. Socarras
Abstract: An adaptive list stores previously received hardware state information that has been used to configure a graphics processing core. One or more filters are configured to filter packets from a packet stream directed to the graphics processing core. The packets are filtered based on a comparison of hardware state information included in the packet and hardware state information stored in the adaptive list. The adaptive list is modified in response to filtering the first packet. The filters can include a hardware filter and a software filter that selectively filters the packets based on whether the graphics processing core is limiting throughput. The adaptive list can be implemented as content-addressable memory (CAM), a cache, or a linked list.
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