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    SYSTEM AND METHOD OF TESTING PROCESSOR UNITS USING CACHE RESIDENT TESTING
    2.
    发明申请
    SYSTEM AND METHOD OF TESTING PROCESSOR UNITS USING CACHE RESIDENT TESTING 审中-公开
    使用高速缓存测试测试处理器单元的系统和方法

    公开(公告)号：US20150286573A1

    公开(公告)日：2015-10-08

    申请号：US14243050

    申请日：2014-04-02

    Applicant: ATI TECHNOLOGIES ULC ,  ADVANCED MICRO DEVICES, INC.

    Inventor： Angel E. Socarras ,  Kostantinos Danny Christidis ,  Curtis Alan Gilgan ,  Alexander Fuad Ashkar

    IPC: G06F12/08

    CPC classification number: G06F12/0875 ,  G06F11/2236 ,  G06F11/2733 ,  G06F11/3037 ,  G06F2212/452 ,  G06F2212/62

    Abstract: Apparatuses, computer readable mediums, and methods of processor unit testing using cache resident testing are disclosed. The method may include loading a test program in a cache on a chip comprising one or more processor units. The method may include the one or more processor units executing the test program to generate one or more results. The method may include redirecting a first memory reference to the cache, wherein the first memory reference is generated during the execution of the test program. The method may include determining whether the one or more generated results match one or more test results. The method may include redirecting a memory request to a memory location resident in the cache if the memory request includes a memory location not resident in the cache. The method may include redirecting a memory request to the cache if the memory request is not directed to the cache.

    Abstract translation: 公开了装置，计算机可读介质和使用高速缓存驻留测试的处理器单元测试的方法。 该方法可以包括将测试程序加载到包括一个或多个处理器单元的芯片上的高速缓存中。 该方法可以包括执行测试程序以生成一个或多个结果的一个或多个处理器单元。 该方法可以包括将第一存储器引用重定向到高速缓存，其中在执行测试程序期间生成第一存储器引用。 该方法可以包括确定一个或多个生成的结果是否匹配一个或多个测试结果。 如果存储器请求包括不驻留在高速缓存中的存储器位置，则该方法可以包括将存储器请求重定向到驻留在高速缓存中的存储器位置。 如果存储器请求没有被指向高速缓存，则该方法可以包括将存储器请求重定向到高速缓存。

    System and method of testing processor units using cache resident testing
    4.
    发明授权
    System and method of testing processor units using cache resident testing 有权

    公开(公告)号：US10198358B2

    公开(公告)日：2019-02-05

    申请号：US14243050

    申请日：2014-04-02

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Angel E. Socarras ,  Kostantinos Danny Christidis ,  Curtis Alan Gilgan ,  Alexander Fuad Ashkar

    IPC: G06F12/0875 ,  G06F11/22 ,  G06F11/30 ,  G06F11/273

    Abstract: Apparatuses, computer readable mediums, and methods of processor unit testing using cache resident testing are disclosed. The method may include loading a test program in a cache on a chip comprising one or more processor units. The method may include the one or more processor units executing the test program to generate one or more results. The method may include redirecting a first memory reference to the cache, wherein the first memory reference is generated during the execution of the test program. The method may include determining whether the one or more generated results match one or more test results. The method may include redirecting a memory request to a memory location resident in the cache if the memory request includes a memory location not resident in the cache. The method may include redirecting a memory request to the cache if the memory request is not directed to the cache.

    Marker-based processor instruction grouping
    5.
    发明授权
    Marker-based processor instruction grouping 有权

    公开(公告)号：US11900123B2

    公开(公告)日：2024-02-13

    申请号：US16713432

    申请日：2019-12-13

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Alexander Fuad Ashkar ,  Manu Rastogi ,  Harry J. Wise

    IPC: G06F9/30 ,  G06F9/38 ,  G06T1/20 ,  G06F15/80

    CPC classification number: G06F9/3869 ,  G06F9/3836 ,  G06F15/80 ,  G06T1/20

    Abstract: A system includes a processing unit such as a GPU that itself includes a command processor configured to receive instructions for execution from a software application. A processor pipeline coupled to the processing unit includes a set of parallel processing units for executing the instructions in sets. A set manager is coupled to one or more of the processor pipeline and the command processor. The set manager includes at least one table for storing a set start time, a set end time, and a set execution time. The set manager determines an execution time for one or more sets of instructions of a first window of sets of instructions submitted to the processor pipeline. Based on the execution time of the one or more sets of instructions, a set limit is determined and applied to one or more sets of instructions of a second window subsequent to the first window.

    Hardware security hardening for processor devices
    6.
    发明授权
    Hardware security hardening for processor devices 有权

    公开(公告)号：US11809558B2

    公开(公告)日：2023-11-07

    申请号：US17032969

    申请日：2020-09-25

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Harry J. Wise ,  Alexander Fuad Ashkar ,  Manu Rastogi

    IPC: G06F21/00 ,  G06F21/56 ,  H04L69/22 ,  G06F9/30 ,  G06F21/54 ,  G06F9/38

    CPC classification number: G06F21/566 ,  G06F9/30076 ,  G06F9/3802 ,  G06F21/54 ,  G06F21/567 ,  H04L69/22

    Abstract: A method of packet attribute confirmation includes receiving, at a command processor of a parallel processor, a command packet including a received packet attribute, such as a packet size, of the command packet. The command processor compares the received packet attribute of the command packet relative to an expected packet attribute of the command packet. The command processor passes one or more commands to a prefetch parser such that a summed total size of the one or more commands is equal to the received packet size of the command packet. The command processor passes, based at least on determining a match between the received packet size and the expected packet size, the received command packet to the prefetch parser. Otherwise, the command processor passes, based at least on determining a mismatch between the received packet size and the expected packet size, one or more no-operation instructions to the prefetch parser.

    Saving power in the command processor using queue based watermarks
    7.
    发明授权
    Saving power in the command processor using queue based watermarks 有权

    公开(公告)号：US10955901B2

    公开(公告)日：2021-03-23

    申请号：US15721109

    申请日：2017-09-29

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Alexander Fuad Ashkar ,  Angel E. Socarras ,  Rex Eldon McCrary

    IPC: G06F1/00 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/3296 ,  G06F1/3287 ,  G06F1/3203

    Abstract: Systems, apparatuses, and methods for dynamically adjusting the power consumption of prefetch engines are disclosed. In one embodiment, a processor includes one or more prefetch engines, a draw completion engine, and a queue in between the one or more prefetch engines and the draw completion engine. If the number of packets stored in the queue is greater than a high watermark, then the processor reduces the power state of the prefetch engine(s). By decreasing the power state of the prefetch engine(s), power consumption is reduced. Additionally, this power consumption reduction is achieved without affecting performance, since the queue has a high occupancy and the draw completion engine can continue to read packets out of the queue. If the number of packets stored in the queue is less than a low watermark, then the processor increases the power state of the prefetch engine(s).

    Suspend and restore processor operations
    8.
    发明授权
    Suspend and restore processor operations 有权

    公开(公告)号：US10558489B2

    公开(公告)日：2020-02-11

    申请号：US15438466

    申请日：2017-02-21

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Alexander Fuad Ashkar ,  Michael J. Mantor ,  Randy Wayne Ramsey ,  Rex Eldon McCrary ,  Harry J. Wise

    IPC: G06F9/48 ,  G06F9/46

    Abstract: Systems, apparatuses, and methods for suspending and restoring operations on a processor are disclosed. In one embodiment, a processor includes at least a control unit, multiple execution units, and multiple work creation units. In response to detecting a request to suspend a software application executing on the processor, the control unit sends requests to the plurality of work creation units to stop creating new work. The control unit waits until receiving acknowledgements from the work creation units prior to initiating a suspend operation. Once all work creation units have acknowledged that they have stopped creating new work, the control unit initiates the suspend operation. Also, when a restore operation is initiated, the control unit prevents any work creation units from launching new work-items until all previously in-flight work-items have been restored to the same work creation units and execution units to which they were previously allocated.

    Content addressable memory with sub-field minimum and maximum clamping
    10.
    发明授权
    Content addressable memory with sub-field minimum and maximum clamping 有权

    公开(公告)号：US11537319B2

    公开(公告)日：2022-12-27

    申请号：US16710563

    申请日：2019-12-11

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Alexander Fuad Ashkar ,  James R. Klobcar ,  Harry J. Wise

    IPC: G06F3/06 ,  G11C15/04

    Abstract: A processing system includes a content addressable memory (CAM) in an input/output path to selectively modify register writes on a per-pipeline basis. The CAM compares an address of a register write to an address field of each entry of the CAM. If a match is found, the CAM modifies the register write data as defined by a function for the matching entry of the CAM. In some embodiments, each entry of the CAM includes a data mask defining subfields of the register write data, wherein each subfield includes subfield data including one or more bits.

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