公开(公告)号：US11444746B1

公开(公告)日：2022-09-13

申请号：US17303757

申请日：2021-06-07

Applicant: Analog Devices, Inc.

Inventor： John Kenney ,  Robert Schell

IPC: H03D3/24 ,  H04L7/00 ,  H03L7/099 ,  H03L7/08 ,  H03K21/08

Abstract: Apparatus and methods for phasing detection of asynchronous dividers are provided herein. In certain embodiments, a clock and data recovery system includes a first divider that outputs a first divided clock signal, a second divider that outputs a second divided clock signal, and an asynchronous clock phasing detection circuit that generates a detection signal indicating a relative phase difference between the first divided clock signal and the second divided clock signal. The asynchronous clock phasing detection circuit includes a quantization and logic circuit that generates an output signal indicating when the first divided clock signal and the second divided clock signal are in different states, an oscillator that outputs a control clock signal, a first counter controlled by the control clock signal and configured to count the output signal, and a control circuit that processes a first count signal from the first counter to generate the detection signal.

公开(公告)号：US11165431B1

公开(公告)日：2021-11-02

申请号：US17116875

申请日：2020-12-09

Applicant: Analog Devices, Inc.

Inventor： John Kenney

IPC: H03L7/081 ,  H03L7/183

Abstract: An apparatus is described and includes a current integrating phase interpolator core having a programmable bias current; an AC-coupled inverter circuit coupled to an output of the current integrating phase interpolator core for receiving a signal comprising a periodic sawtooth waveform therefrom; a digital-to-analog (D/A) converter for setting an input common mode voltage of the AC-coupled inverter circuit; a duty cycle measurement (DCM) circuit for measuring a duty cycle distortion (DCD) of a rectangular wave clock signal output from the AC-coupled inverter circuit; and a circuit for computing a difference in the DCD of the rectangular wave clock signal when the input common mode voltage of the AC-coupled inverter circuit is set to a high voltage and when the input common mode voltage of the AC-coupled inverter circuit is set to a low voltage.

公开(公告)号：US09184909B1

公开(公告)日：2015-11-10

申请号：US14594472

申请日：2015-01-12

Applicant: Analog Devices, Inc.

Inventor： Stuart McCracken ,  John Kenney ,  Kimo Tam

IPC: H04L7/04 ,  H04L7/00 ,  H04L7/02

CPC classification number: H04L7/0337 ,  H03L7/0807 ,  H03L7/0814 ,  H03L7/087 ,  H03L7/091 ,  H04L7/0008 ,  H04L7/002 ,  H04L7/0033 ,  H04L7/02 ,  H04L7/042 ,  H04L25/14

Abstract: Apparatus and methods for clock and data recovery (CDR) are provided herein. In certain configurations, a first CDR circuit captures data and edge samples from a first input data stream received over a first lane. The data and edge samples are used to generate a master phase signal, which is used to control a phase of a first data sampling clock signal used for capturing the data samples. Additionally, the first CDR circuit generates a master phase error signal based on changes to the master phase signal over time, and forwards the master phase error signal to at least a second CDR circuit. The second CDR circuit processes the master phase error signal to generate a slave phase signal used to control a phase of a second data sampling clock signal used for capturing data samples from a second input data stream received over a second lane.

Abstract translation: 本文提供了用于时钟和数据恢复（CDR）的装置和方法。 在某些配置中，第一CDR电路从在第一通道上接收的第一输入数据流捕获数据和边缘样本。 数据和边缘采样用于产生主相位信号，其用于控制​​用于捕获数据样本的第一数据采样时钟信号的相位。 此外，第一CDR电路基于随着时间的主相位信号的改变而产生主相位误差信号，并将主相位误差信号转发到至少第二CDR电路。 第二CDR电路处理主相位误差信号以产生用于控制用于从通过第二通道接收的第二输入数据流捕获数据样本的第二数据采样时钟信号的相位的从相信号。