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    Partial voltage read of memory
    11.
    发明授权
    Partial voltage read of memory 有权
    内存的部分电压读数

    公开(公告)号：US09202573B2

    公开(公告)日：2015-12-01

    申请号：US14168219

    申请日：2014-01-30

    Applicant: Apple Inc.

    Inventor： Michael J. Cornwell ,  Christopher P. Dudte

    IPC: G06F11/00 ,  G11C16/06 ,  G06F11/10 ,  G11C16/26 ,  G11C29/04

    CPC classification number: G11C16/06 ,  G06F11/1068 ,  G11C16/26 ,  G11C2029/0411

    Abstract: A partial voltage level read is made on memory cells of a solid state memory device during a voltage settling time after the memory cells are charged (e.g., by a pulse from a charge pump). Digital values representing partial voltage levels are checked for errors (e.g., by an error correction code (ECC) engine). If the values can be corrected, then the values are released for host access. If the values cannot be corrected, then a full voltage read is performed on the memory cells after the voltage levels have substantially settled. Digital values corresponding to the full voltage reads can be released for host access. The use of partial voltage reads results in faster read of solid state memory devices.

    Abstract translation: 在存储器单元被充电之后的电压建立时间（例如，通过来自电荷泵的脉冲）期间，在固态存储器件的存储器单元上进行部分电压电平读取。 检查表示部分电压电平的数字值是否存在错误（例如，通过纠错码（ECC）引擎）。 如果可以更正这些值，则释放主机访问的值。 如果这些值无法校正，则在电压电平基本稳定后，对存储单元执行全电压读取。 可以释放与全电压读数相对应的数字值，以进行主机访问。 使用部分电压读数可以更快地读取固态存储器件。

    SWITCHING DRIVERS BETWEEN PROCESSORS
    13.
    发明申请
    SWITCHING DRIVERS BETWEEN PROCESSORS 有权
    处理器之间切换驱动程序

    公开(公告)号：US20130185481A1

    公开(公告)日：2013-07-18

    申请号：US13729504

    申请日：2012-12-28

    Applicant: APPLE INC.

    Inventor： Michael J. Cornwell ,  Christopher P. Dudte

    IPC: G06F9/44 ,  G06F12/02

    CPC classification number: G06F9/441 ,  G06F9/30032 ,  G06F9/3877 ,  G06F12/0246

    Abstract: Systems, methods, and computer software for operating a device can be used to operate the device in multiple modes. The device can be operated in a first operating mode adapted for processing data, in which a first processor executes a driver for a nonvolatile memory and a second processor performs processing of data stored in files on the nonvolatile memory. An instruction can be received to switch the device to a second operating mode adapted for reading and/or writing files from or to the nonvolatile memory. The driver for the nonvolatile memory can be switched from the first processor to the second processor in response to the instruction, and the driver for the nonvolatile memory can be executed on the second processor after performing the switch. A communications driver can be executed on the first processor in response to the instruction to switch the device to the second operating mode.

    Abstract translation: 用于操作设备的系统，方法和计算机软件可用于以多种模式操作设备。 该装置可以在适于处理数据的第一操作模式中操作，其中第一处理器执行用于非易失性存储器的驱动器，并且第二处理器执行存储在非易失性存储器上的文件中的数据的处理。 可以接收指令以将设备切换到适于从非易失性存储器读取和/或写入文件的第二操作模式。 用于非易失性存储器的驱动器可以响应于该指令从第一处理器切换到第二处理器，并且可以在执行开关之后在第二处理器上执行用于非易失性存储器的驱动器。 响应于将设备切换到第二操作模式的指令，可以在第一处理器上执行通信驱动器。

    Dynamic cell state resolution
    14.
    发明申请
    Dynamic cell state resolution 审中-公开
    动态单元状态分辨率

    公开(公告)号：US20150380083A1

    公开(公告)日：2015-12-31

    申请号：US14716574

    申请日：2015-05-19

    Applicant: Apple Inc.

    Inventor： Michael J. Cornwell ,  Christopher P. Dudte

    IPC: G11C11/56 ,  G11C16/04

    CPC classification number: G11C11/5628 ,  G11C5/04 ,  G11C5/145 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/24 ,  G11C16/30 ,  G11C29/78

    Abstract: A system and method for storing data uses multiple flash memory dies. Each flash memory die includes multiple flash memory cells. A charge pump is adapted to supply charge at a predetermined voltage to each flash memory die of the flash memory dies, and an interface is adapted to receive instructions for controlling the charge pump.

    Abstract translation: 用于存储数据的系统和方法使用多个闪速存储器管芯。 每个闪存芯片包括多个闪存单元。 电荷泵适于以预定电压向闪存芯片的每个闪速存储器管芯提供电荷，并且接口适于接收用于控制电荷泵的指令。

    Initiating Memory Wear Leveling
    17.
    发明申请
    Initiating Memory Wear Leveling 审中-公开
    启动内存容量调整

    公开(公告)号：US20140136771A1

    公开(公告)日：2014-05-15

    申请号：US14160763

    申请日：2014-01-22

    Applicant: Apple Inc.

    Inventor： Michael J. Cornwell ,  Christopher P. Dudte ,  Nir Jacob Wakrat

    IPC: G06F12/02

    CPC classification number: G06F12/0246 ,  G06F12/0253 ,  G06F2212/1016 ,  G06F2212/7211

    Abstract: Systems and processes may use a host and an external host. The host may be a portable device that includes a memory, a memory controller, and a communication interface for communication with the external host. The portable device may receive a command signal from the external host and initiate a predetermined amount of wear leveling in response to the command signal.

    Abstract translation: 系统和进程可以使用主机和外部主机。 主机可以是包括存储器，存储器控制器和用于与外部主机通信的通信接口的便携式设备。 便携式设备可以从外部主机接收命令信号，并响应于命令信号启动预定量的磨损均衡。

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