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公开(公告)号：US09946101B2
公开(公告)日：2018-04-17
申请号：US14835366
申请日：2015-08-25
Applicant: Apple Inc.
Inventor： James E. C. Brown , Fenghua Zheng , Sandro H. Pintz
CPC classification number: G02F1/13306 , G09G3/3677 , G09G2310/0286 , G09G2310/0289
Abstract: A method for operating a gate driver that is driving pixel transistors of a display panel, is described. An internal start pulse is produced in response to an external start pulse and in accordance with a system clock, wherein the internal start pulse is input to a first cell of a gate driver shift register whose outputs are coupled to level shifting output stages that are driving the rows of pixel transistors of the display panel. The produced internal start pulse was qualified by an output of a last cell of the gate driver shift register. Other embodiments are also described and claimed.
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12.发明申请公开(公告)号：US20160300546A1
公开(公告)日：2016-10-13
申请号：US14855733
申请日：2015-09-16
Applicant: Apple Inc.
Inventor： Fenghua Zheng , Christopher P. Tann , David S. Zalatimo , James E. C. Brown , Sandro H. Pintz
IPC: G09G5/00
CPC classification number: G09G3/2096 , G09G3/20 , G09G2310/0267 , G09G2310/0286 , G09G2310/0289 , G09G2310/06 , G09G2310/08 , G09G2330/021
Abstract: A display may have an array of pixels controlled by display driver circuitry. Gate driver circuitry supplies gate line signals to rows of the pixels. The gate driver circuitry may include gate driver integrated circuits. Each gate driver integrated circuit may have a shift register that supplies the gate line signals to the rows of pixels. The display driver circuitry supplies a clock signal to the gate driver integrated circuits. Each gate driver integrated circuit may have one or more clock trees that are selectively enable and disabled. Each gate driver integrated circuit may have a controller and a buffer that is controlled by a control signal from the controller. The buffer may be adjusted to supply or to not supply the clock signal to an associated clock tree in that gate driver integrated circuit.
Abstract translation: 显示器可以具有由显示驱动器电路控制的像素阵列。 栅极驱动器电路将栅极线信号提供给像素的行。 栅极驱动器电路可以包括栅极驱动器集成电路。 每个栅极驱动器集成电路可以具有将栅极线信号提供给像素行的移位寄存器。 显示驱动器电路将时钟信号提供给栅极驱动器集成电路。 每个栅极驱动器集成电路可以具有选择性地使能和禁止的一个或多个时钟树。 每个栅极驱动器集成电路可以具有由来自控制器的控制信号控制的控制器和缓冲器。 可以调整缓冲器以提供或不向该栅极驱动器集成电路中的相关联的时钟树提供时钟信号。
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13.发明申请METHOD AND APPARATUS FOR SIMPLIFYING COMMUNICATION BETWEEN A HOST SYSTEM AND A DISPLAY SUBSYSTEM 有权用于简化主机系统和显示器子系统之间的通信的方法和装置公开(公告)号：US20150199292A1
公开(公告)日：2015-07-16
申请号：US14500944
申请日：2014-09-29
Applicant: Apple Inc.
Inventor： David W. Lum , Thomas J. Wilson , Paolo Sacchetto , Sandro H. Pintz , Fenghua Zheng
CPC classification number: G06F13/4221
Abstract: A method for simplifying the host-to-display subsystem communications and consolidating the non-volatile memory requirements into a PMIC (power management integrated circuit) is disclosed. Hardware and software resource reduction in both the client devices (located in the display subsystem) and the host System on a Chip (SOC) can be realized with a novel PMIC design. The novel PMIC design achieves the resource reduction by providing for the following features: (1) Single-point communication, (2) Single-point notification, (3) Client device status storage, (4) Client device initialization from PMIC non-volatile memory, and (5) Subsystem calibration retrieval from PMIC non-volatile memory.
Abstract translation: 公开了一种用于简化主机到显示器子系统通信并将非易失性存储器需求整合到PMIC（电力管理集成电路）中的方法。 可以通过新颖的PMIC设计来实现客户端设备（位于显示子系统中）和主机片上系统（SOC）的硬件和软件资源减少。 新型PMIC设计通过提供以下特点实现资源减少：（1）单点通信，（2）单点通知，（3）客户端设备状态存储，（4）PMIC非易失性的客户端设备初始化 存储器和（5）PMIC非易失性存储器的子系统校准检索。
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公开(公告)号：US20250095540A1
公开(公告)日：2025-03-20
申请号：US18815162
申请日：2024-08-26
Applicant: Apple Inc.
Inventor： Vehbi Calayir , Weimin Zhang , Bret Rothenberg , Zhongyuan Ren , Fenghua Zheng , Mohammad Reza Esmaeili Rad
IPC: G09G3/20
Abstract: A power management integrated circuit (PMIC) of an electronic display may include image data reference voltage adjustment circuitry, a negative supply voltage generator that may generate a negative supply voltage with multiple negative supply voltages, and/or a dedicated timing controller. The image data reference voltage adjustment circuitry may tune image data reference voltages for generating programming voltages based on receiving an indication of an undesired direct current (DC) voltage offset, an undesired alternating current (AC) noise, or both. The image data reference voltage adjustment circuitry may receive the indication from a display panel of the electronic display. The negative supply voltage generator may elevate a voltage of the negative supply voltage to reduce a power consumption of the electronic display. The dedicated timing controller may improve (e.g., reduce length of) a frequency range of one or more switched voltages of the PMIC to reduce front of screen artifacts.
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公开(公告)号：US20220059018A1
公开(公告)日：2022-02-24
申请号：US17406012
申请日：2021-08-18
Applicant: Apple Inc.
Inventor： Shatam Agarwal , Sean C. Chang , Hao-Lin Chiu , Fenghua Zheng , Pierre-Yves Emelie , Yao Chen , Marc Albrecht , Mingxia Gu , Jun Qi , Wei Chen
IPC: G09G3/32
Abstract: A light emitting diode (LED) display can calculate a common voltage charge of a line of pixels in the LED display, the common voltage charge comprising a difference between a first line of pixels and a second line of pixels. If the calculated common voltage charge exceeds a predetermined threshold, a toggle matrix can be generated for the line of pixels. The toggle matrix can include a matrix of charge values generated by calculating a difference in charge values for each subpixel a first line of subpixels with each subpixel a second line of subpixels. The LED display can identify one or more regions of subpixels exhibiting the predetermined toggle pattern in the toggle matrix. The LED display can generate a voltage correction charge to apply to affected regions of the display. Alternatively, the subpixels or pixels could be swapped with adjacent pixels to reduce toggling or settling error.
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Patent Agency Ranking
公开(公告)号：US10600379B2
公开(公告)日：2020-03-24
申请号：US16103852
申请日：2018-08-14
Applicant: Apple Inc.
Inventor： Prasanna Nambi , Jason N. Gomez , Fenghua Zheng , Paolo Sacchetto , Sandro H. Pintz , Taesung Kim , Christopher P. Tann , Marc Albrecht , David W. Lum
Abstract: The disclosure describes procedures for dynamically employing a variable refresh rate at an LCD display of a consumer electronic device, such as a laptop computer, a tablet computer, a mobile phone, or a music player device. In some configurations, the consumer electronic device can include a host system portion, having one or more processors and a display system portion, having a timing controller, a buffer circuit, a display driver, and a display panel. The display system can receive image data and image control data from a GPU of the host system, evaluate the received image control data to determine a reduced refresh rate (RRR) for employing at the display panel, and then transition to the RRR, whenever practicable, to conserve power. In some scenarios, the transition to the RRR can be a transition from a LRR of 50 hertz or above to a RRR of 40 hertz or below.
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公开(公告)号：US09984608B2
公开(公告)日：2018-05-29
申请号：US14986181
申请日：2015-12-31
Applicant: Apple Inc.
Inventor： Paolo Sacchetto , Christopher P. Tann , Taesung Kim , Sandro H. Pintz , Marc Albrecht , Chaohao Wang , David S. Zalatimo , Fenghua Zheng , Zhibing Ge
CPC classification number: G09G3/20 , G09G2310/0254 , G09G2310/063 , G09G2310/08 , G09G2320/0204 , G09G2340/0435
Abstract: System and method for improving displayed image quality of an electronic display that displays a first image frame by applying a first voltage to a display pixel and a second image frame directly before the first image frame by applying a second voltage to the display pixel. A display pipeline is communicatively coupled to the electronic display and receives first image data corresponding with the first image frame, where the image data includes a first grayscale value corresponding with the display pixel. Additionally the display pipeline determines an inversion balancing grayscale offset based at least in part on the first grayscale value when polarity of the first voltage and polarity of the second voltage are the same and determines magnitude of the first voltage by applying the inversion balancing grayscale offset to the first grayscale value to reduce likelihood of a perceivable luminance spike when displaying the first image frame.
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公开(公告)号：US20160267865A1
公开(公告)日：2016-09-15
申请号：US14835366
申请日：2015-08-25
Applicant: Apple Inc.
Inventor： James E.C. Brown , Fenghua Zheng , Sandro H. Pintz
CPC classification number: G02F1/13306 , G09G3/3677 , G09G2310/0286 , G09G2310/0289
Abstract: A method for operating a gate driver that is driving pixel transistors of a display panel, is described. An internal start pulse is produced in response to an external start pulse and in accordance with a system clock, wherein the internal start pulse is input to a first cell of a gate driver shift register whose outputs are coupled to level shifting output stages that are driving the rows of pixel transistors of the display panel. The produced internal start pulse was qualified by an output of a last cell of the gate driver shift register. Other embodiments are also described and claimed.
Abstract translation: 描述了用于操作正在驱动显示面板的像素晶体管的栅极驱动器的方法。 响应于外部起始脉冲并根据系统时钟产生内部起始脉冲，其中内部起始脉冲被输入到栅极驱动器移位寄存器的第一单元，栅极驱动器移位寄存器的输出耦合到正在驱动的电平移位输出级 显示面板的像素晶体管行。 产生的内部起始脉冲由栅极驱动器移位寄存器的最后一个单元的输出限定。 还描述和要求保护其他实施例。
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公开(公告)号：US20140198114A1
公开(公告)日：2014-07-17
申请号：US14155292
申请日：2014-01-14
Applicant: Apple Inc.
Inventor： Prasanna Nambi , Jason N. Gomez , Fenghua Zheng , Paolo Sacchetto , Sandro H. Pintz , Taesung Kim , Christopher P. Tann , Marc Albrecht , David W. Lum
IPC: G09G3/36
CPC classification number: G09G3/3618 , G06T1/20 , G06T2210/52 , G09G3/36 , G09G3/3611 , G09G3/3648 , G09G3/3655 , G09G3/3696 , G09G2310/08 , G09G2320/0626 , G09G2330/02 , G09G2330/021 , G09G2340/0435 , G09G2360/18 , G09G2370/08
Abstract: The disclosure describes procedures for dynamically employing a variable refresh rate at an LCD display of a consumer electronic device, such as a laptop computer, a tablet computer, a mobile phone, or a music player device. In some configurations, the consumer electronic device can include a host system portion, having one or more processors and a display system portion, having a timing controller, a buffer circuit, a display driver, and a display panel. The display system can receive image data and image control data from a GPU of the host system, evaluate the received image control data to determine a reduced refresh rate (RRR) for employing at the display panel, and then transition to the RRR, whenever practicable, to conserve power. In some scenarios, the transition to the RRR can be a transition from a LRR of 50 hertz or above to a RRR of 40 hertz or below.
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公开(公告)号：US11099804B2
公开(公告)日：2021-08-24
申请号：US16529705
申请日：2019-08-01
Applicant: Apple Inc.
Inventor： Fenghua Zheng , David S. Zalatimo , James E. Brown , Sachiko Oda , Johan L. Piper
Abstract: Aspects of the subject technology relate to electronic device display circuitry and methods of operating the display. The display circuitry a panel driver interface that decodes digital display data, for each display frame, received from host circuitry of the electronic device. The digital display data includes error correction and detection information for frame and line configuration information distributed in a frame packet and multiple line packets for each display frame. The frame and line configuration information facilitates, efficient, low-error, digital control of various display operational features.
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