Link aggregator for an electronic display

    公开(公告)号:US10699363B2

    公开(公告)日:2020-06-30

    申请号:US15627192

    申请日:2017-06-19

    Applicant: Apple Inc.

    Abstract: Video data and auxiliary data may be sent between a processor and a display device via a single cable using a link aggregator. As such, the link aggregator may receive a first parallel signal that may include the video data and a second parallel signal that may include auxiliary data from the processor. The link aggregator may then send the first parallel signal and the second parallel signal as an aggregated signal to the display device. Upon receiving the aggregated signal at the display device, the link aggregator may de-aggregate the aggregated signal into the first parallel signal and the second parallel signal. The link aggregator may then send the first parallel signal and the second parallel signal to a timing controller of the display device, such that the timing controller may display the video data using the display device.

    Methods and apparatus for multi-lane mapping, link training and lower power modes for a high speed bus interface

    公开(公告)号:US10523867B2

    公开(公告)日:2019-12-31

    申请号:US15620595

    申请日:2017-06-12

    Applicant: Apple Inc.

    Abstract: Methods and apparatus for link training and low power operation. A multi-lane high speed bus is optimized for transferring audio/visual (A/V) data at slower rates. In one embodiment, the high speed bus is configured to use a packet format structure that allows for more fluid data delivery times, thereby allowing the high speed bus to deliver A/V data at times selected to reduce power consumption. In another embodiment, the high speed bus is configured to cache link initialization data for subsequent link re-initialization before entering a low power state. Thereafter, when the link exits the low power state, the high speed bus can skip certain portions of link initialization. Still a third embodiment of the present disclosure is directed to exemplary modifications to existing high speed bus link training and low power operation, consistent with the aforementioned principles. Variants of a Universal Serial Bus implementation are provided for illustration.

    Link aggregator for an electronic display

    公开(公告)号:US09684942B2

    公开(公告)日:2017-06-20

    申请号:US14024428

    申请日:2013-09-11

    Applicant: APPLE INC.

    CPC classification number: G06T1/20 G09G5/006 G09G2352/00 G09G2370/12

    Abstract: Video data and auxiliary data may be sent between a processor and a display device via a single cable using a link aggregator. As such, the link aggregator may receive a first parallel signal that may include the video data and a second parallel signal that may include auxiliary data from the processor. The link aggregator may then send the first parallel signal and the second parallel signal as an aggregated signal to the display device. Upon receiving the aggregated signal at the display device, the link aggregator may de-aggregate the aggregated signal into the first parallel signal and the second parallel signal. The link aggregator may then send the first parallel signal and the second parallel signal to a timing controller of the display device, such that the timing controller may display the video data using the display device.

    SHARING A GRAPHICS-PROCESSING-UNIT DISPLAY PORT
    16.
    发明申请
    SHARING A GRAPHICS-PROCESSING-UNIT DISPLAY PORT 审中-公开
    共享一个图形处理单元显示端口

    公开(公告)号:US20150286455A1

    公开(公告)日:2015-10-08

    申请号:US14746623

    申请日:2015-06-22

    Applicant: Apple Inc.

    Abstract: An electronic device selectively couples a head with links in a graphics processing unit to a currently selected display port in a pair of display ports. During operation, control logic in the electronic device monitors a pair of configuration signals from the pair of display ports, where the pair of configuration signals correspond to physical connections to the pair of display ports. Then, the control logic determines a selection control signal based on the monitored pair of configuration signals, a policy setting and a default display port, where the selection control signal specifies the currently selected display port. Moreover, the control logic provides the selection control signal to a multiplexer in the electronic device. Next, the multiplexer selectively couples the head with the links in the graphics processing unit to the currently selected display port based on the selection control signal.

    Abstract translation: 电子设备将头部与图形处理单元中的链路选择性地耦合到一对显示端口中的当前选择的显示端口。 在操作期间,电子设备中的控制逻辑监视来自该对显示端口的一对配置信号,其中该对配置信号对应于到该对显示端口的物理连接。 然后,控制逻辑基于所监视的一对配置信号,策略设置和默认显示端口来确定选择控制信号,其中选择控制信号指定当前选择的显示端口。 此外,控制逻辑将选择控制信号提供给电子设备中的多路复用器。 接下来,多路复用器基于选择控制信号将头部与图形处理单元中的链路选择性地耦合到当前选择的显示端口。

    METHODS AND APPARATUS FOR VIRTUAL CHANNEL ALLOCATION VIA A HIGH SPEED BUS INTERFACE
    17.
    发明申请
    METHODS AND APPARATUS FOR VIRTUAL CHANNEL ALLOCATION VIA A HIGH SPEED BUS INTERFACE 有权
    通过高速总线接口进行虚拟通道分配的方法和设备

    公开(公告)号:US20150205749A1

    公开(公告)日:2015-07-23

    申请号:US14566454

    申请日:2014-12-10

    Applicant: APPLE INC.

    Abstract: Methods and apparatus for virtual channel allocation within an electronic device. In one exemplary embodiment, the device is a consumer electronics device having multiple camera sensors uses a modified high-speed protocol (e.g., DisplayPort Multi-Stream Transport (MST) protocol) to process camera data via one or more virtual channels. Unlike traditional solutions which rely on an intelligent source device to manage a network of devices, the present disclosure describes in one aspect a network of nodes internal to a consumer electronic device that is managed by the sink node (i.e., a “smart sink”). Additionally, since the full suite of protocol (e.g., DisplayPort) capabilities are unnecessary for certain design scenarios, certain further disclosed simplifications improve performance for sink nodes having very modest capabilities.

    Abstract translation: 电子设备内虚拟信道分配的方法和装置。 在一个示例性实施例中,设备是具有使用修改的高速协议(例如,DisplayPort多流传输(MST)协议))的多个摄像机传感器的消费电子设备经由一个或多个虚拟通道来处理照相机数据。 不同于依赖于智能源设备来管理设备网络的传统解决方案,本公开在一个方面描述了由宿节点(即,“智能宿”)管理的消费电子设备内部节点的网络, 。 另外,由于对于某些设计场景,全套协议(例如,DisplayPort)功能是不必要的,所以某些进一步公开的简化可以改善具有非常适中能力的汇聚节点的性能。

    Ultra-low latency audio over bluetooth

    公开(公告)号:US11259192B2

    公开(公告)日:2022-02-22

    申请号:US16146138

    申请日:2018-09-28

    Applicant: Apple Inc.

    Abstract: Methods and apparatus for communicating audio packets with ultra-low latency at high data rates from an audio source device to one or more audio output devices over a wireless personal area network (WPAN) connection, such as via a Bluetooth connection. Latency is reduced by using time-efficient audio coding and decoding, limited retransmissions, reduced time and frequency of acknowledgements, and by combining Bluetooth Classic (BTC) packets for downlink audio and downlink control with Bluetooth Low Energy (BTLE) packets for uplink control, uplink acknowledgements, and inter-device wireless communication. The number of retransmissions and packet concealments per frame cycle can be limited to an upper threshold number to satisfy a low latency requirement.

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