公开(公告)号：US09612949B2

公开(公告)日：2017-04-04

申请号：US13916722

申请日：2013-06-13

Applicant: ARM Limited

Inventor： Oskar Flordal ,  Hakan Persson ,  Andreas Engh-Halstvedt

IPC: G06F12/00 ,  G06F12/02 ,  G06F9/50 ,  G06T1/60

CPC classification number: G06F12/02 ,  G06F9/5016 ,  G06F12/0284 ,  G06T1/60

Abstract: A processing system comprises plural processing cores and a task allocator for allocating tasks to the processing cores. The processing cores perform the tasks that are allocated to them so as to produce results for the tasks, the results being stored by the processing cores in a buffer. The task allocator indicates to the processing cores memory portions within the buffer in which to store the results. When the processing cores determine that a given memory portion is becoming full, the processing cores request that the task allocator indicates a new memory portion in which to store its results. The processing system allows the task allocator to dynamically and efficiently allocate memory portions to plural processing cores without the task allocator 40 needing to know the sizes of the results being produced by the processing cores.

公开(公告)号：US09092345B2

公开(公告)日：2015-07-28

申请号：US13962905

申请日：2013-08-08

Applicant: ARM Limited

Inventor： Jorn Nystad ,  Andreas Engh-Halstvedt

IPC: G06F12/08 ,  G06F9/30 ,  G06F9/38 ,  G06T1/20 ,  G06T1/60

CPC classification number: G06F12/0875 ,  G06F9/3004 ,  G06F9/3824 ,  G06F9/3828 ,  G06F9/3834 ,  G06F9/3851 ,  G06F9/3887 ,  G06F12/0815 ,  G06F12/0842 ,  G06T1/60

Abstract: A data processing system includes one or more processors 4, 5, 6, 7 operable to initiate atomic memory requests for execution threads and plural data caches 8, 9, 10, 11 that are used to store data needed to perform an atomic memory operation when an atomic memory operation is to be performed.When atomic operations are to be performed against a data cache, the results of atomic operations that are to access the same memory location are accumulated in a temporary cache line in the data cache pending the arrival in the cache of the “true” cache line from memory. The accumulated results of the atomic operations stored in the temporary cache line are then combined with the cache line from memory when the cache line arrives in the cache. Individual atomic values can also be reconstructed once the cache line arrives at the cache.

Abstract translation: 数据处理系统包括一个或多个处理器4,5,6,7，其可操作以发起用于执行线程的原子存储器请求以及用于存储执行原子存储器操作所需的数据的多个数据高速缓存8,9,10,11， 将执行原子存储器操作。 当要针对数据高速缓存执行原子操作时，访问同一内存位置的原子操作的结果将累积在数据高速缓存中的临时高速缓存行中，等待到达“真”高速缓存行的高速缓存中 记忆。 然后，当高速缓存行到达高速缓存时，存储在临时高速缓存行中的原子操作的累积结果与来自存储器的高速缓存行组合。 一旦高速缓存行到达高速缓存，也可以重构单个原子值。

公开(公告)号：US20130076762A1

公开(公告)日：2013-03-28

申请号：US13623751

申请日：2012-09-20

Applicant: ARM Limited

Inventor： Frode Heggelund ,  Aske Simon Christensen ,  Andreas Engh-Halstvedt

IPC: G06T1/20 ,  G06T1/00

CPC classification number: G06T1/20 ,  G06T1/00 ,  G06T11/40

Abstract: The fragment processing pipeline 10 of a graphics processing core 2 has an associated occlusion query cache 19 that is used to maintain a set of local occlusion counters 21. The occlusion query cache 19 is maintained in a local memory 3 of the graphics processing system and can communicate via an interconnect 7 with a set of master occlusion counters 22 in a main memory 5 for the graphics processing system. When an occlusion query starts, a corresponding occlusion counter 22 is initialised in the main memory 5. A corresponding local occlusion counter 21 is also provided in the occlusion query cache 19 in the local memory 3 of the graphics processor, and is used to count the results of the occlusion query. The local occlusion counter value is written back to the occlusion counter 22 for the query in the main memory 5 at the appropriate time for further processing.

Abstract translation: 图形处理核心2的片段处理流水线10具有关联的遮挡查询高速缓存19，其用于维护一组局部遮挡计数器21.遮挡查询高速缓存19被保存在图形处理系统的本地存储器3中，并且可以 通过互连7与用于图形处理系统的主存储器5中的一组主遮挡计数器22进行通信。 当闭塞查询开始时，在主存储器5中初始化对应的遮挡计数器22.在图形处理器的本地存储器3中的遮挡查询高速缓存19中还提供相应的局部遮挡计数器21，并且用于计数 闭塞查询的结果。 局部遮挡计数器值在适当的时间被写回到主存储器5中的查询的遮挡计数器22用于进一步处理。

公开(公告)号：US11003489B2

公开(公告)日：2021-05-11

申请号：US15125661

申请日：2015-03-11

Applicant: ARM Limited

Inventor： Robert Elliott ,  Vatsalya Prasad ,  Andreas Engh-Halstvedt

IPC: G06F9/48 ,  G06F9/38 ,  G06F9/54

Abstract: A microprocessor system (1) includes a host processor (2), a graphics processing unit (GPU) (3) that includes a number of processing cores (4), and an exception handler. When a thread that is executing on a processing core (4) encounters an exception in its instruction sequence, the thread is redirected to the exception handler. However, the exception event is also communicated to a task manager (5) of the GPU 3. The task manager (5) then broadcasts a cause exception message to each processing core (4). Each processing core then identifies the threads that it is currently executing that the cause exception message relates to, and redirects those threads to the exception handler. In this way, an exception caused by a single thread is broadcast to all threads within a task.

公开(公告)号：US09965827B2

公开(公告)日：2018-05-08

申请号：US14796979

申请日：2015-07-10

Applicant: ARM Limited

Inventor： Simon Charles ,  Andreas Engh-Halstvedt

IPC: G06T1/60 ,  G06T1/20 ,  G06F12/08 ,  G06F12/12 ,  G06F12/02 ,  G06F12/0864 ,  G06F12/0895 ,  G06F12/128

CPC classification number: G06T1/60 ,  G06F12/02 ,  G06F12/0864 ,  G06F12/0895 ,  G06F12/128 ,  G06F2212/6032 ,  G06F2212/621 ,  G06T1/20

Abstract: A graphics processing system for processing polygons includes a cache with cache lines for storing data entries, each line having a tag for identifying the data stored in the line. The polygons have vertices with which pieces of vertex attribute data are associated. The system also includes processing circuitry which writes, to a line in a first set of lines, data entries associated with pieces of vertex attribute data. The pieces of vertex attribute data are associated with the vertices of a polygon. The processing circuitry also writes a tag including a polygon identifier to identify the polygon associated with the data entries to the line in the first set of lines, and writes, to a second set of lines of the cache, data entries associated with pieces of vertex attribute data. The processing circuitry also writes tags including vertex identifiers to the second set of lines to identify the vertices associated with the data entries.

公开(公告)号：US09659401B2

公开(公告)日：2017-05-23

申请号：US13690159

申请日：2012-11-30

Applicant: ARM Limited

Inventor： Jorn Nystad ,  Andreas Engh-Halstvedt ,  Edvard Sorgard ,  Thomas Jeremy Olson ,  Marius Bjorge

IPC: G06T15/04 ,  G06T11/40

CPC classification number: G06T15/04 ,  G06T11/40

Abstract: A graphics virtual texturing system in which textures stored in a storage medium of a host system are divided into respective pages that are then loaded into a local memory of a graphics processing system for use. Each page of a graphics texture has an associated fade factor value that can be set by an application that is to use the texture to control the contribution that the page will be used to make to any texturing result that is generated using the texture page in question. The graphics processing system then controls the contribution of texture data from a texture page to texturing result data to be generated in accordance with the fade factor value associated with the texture page in question. This allows texture paging to be done in a more visually pleasing manner than just a binary “page-is-here”/“page-is-not-here” switch.

公开(公告)号：US20160196633A1

公开(公告)日：2016-07-07

申请号：US14796979

申请日：2015-07-10

Applicant: ARM LIMITED

Inventor： Simon Charles ,  Andreas Engh-Halstvedt

IPC: G06T1/60 ,  G06F12/08 ,  G06T1/20 ,  G06F12/12

CPC classification number: G06T1/60 ,  G06F12/02 ,  G06F12/0864 ,  G06F12/0895 ,  G06F12/128 ,  G06F2212/6032 ,  G06F2212/621 ,  G06T1/20

Abstract: A graphics processing system for processing polygons includes a cache with cache lines for storing data entries, each line having a tag for identifying the data stored in the line. The polygons have vertices with which pieces of vertex attribute data are associated. The system also includes processing circuitry which writes, to a line in a first set of lines, data entries associated with pieces of vertex attribute data. The pieces of vertex attribute data are associated with the vertices of a polygon. The processing circuitry also writes a tag including a polygon identifier to identify the polygon associated with the data entries to the line in the first set of lines, and writes, to a second set of lines of the cache, data entries associated with pieces of vertex attribute data. The processing circuitry also writes tags including vertex identifiers to the second set of lines to identify the vertices associated with the data entries.

Abstract translation: 用于处理多边形的图形处理系统包括具有用于存储数据条目的高速缓存行的高速缓存，每行具有用于识别存储在该行中的数据的标签。 多边形具有与哪些顶点属性数据相关联的顶点。 该系统还包括处理电路，其向第一组行中的行写入与多个顶点属性数据相关联的数据条目。 顶点属性数据与多边形的顶点相关联。 处理电路还写入包括多边形标识符的标签，以将与数据条目相关联的多边形标识到第一组行中的行，并且将高速缓存的第二组行写入与多个顶点相关联的数据条目 属性数据。 处理电路还将包括顶点标识符的标签写入第二组线以识别与数据条目相关联的顶点。

公开(公告)号：US20160005140A1

公开(公告)日：2016-01-07

申请号：US14790452

申请日：2015-07-02

Applicant: ARM Limited

Inventor： Andreas Engh-Halstvedt ,  Daren Croxford ,  Frank Langtind

IPC: G06T1/20

CPC classification number: G06T15/005

Abstract: A graphics processing pipeline (20) comprises first vertex shading circuitry (21) that operates to vertex shade position attributes of vertices of a set of vertices to be processed by the graphics processing pipeline. Tiling circuitry (22) then determines for the vertices that have been subjected to the first vertex shading operation, whether the vertices should be processed further. A second vertex shading circuitry (23) then performs a second vertex shading operation on the vertices that it has been determined should be processed further, to vertex shade the remaining vertex attributes for each vertex that it has been determined should be processed further.

Abstract translation: 图形处理流水线（20）包括第一顶点着色电路（21），其操作以由图形处理流水线处理的一组顶点的顶点的顶点颜色位置属性。 平铺电路（22）然后确定已经经受第一顶点着色操作的顶点，是否应进一步处理顶点。 然后，第二顶点着色电路（23）对顶点执行第二顶点着色操作，以确定应进一步处理顶点着色操作，以便顶点遮蔽其应确定的每个顶点的剩余顶点属性应进一步处理。

公开(公告)号：US20150062154A1

公开(公告)日：2015-03-05

申请号：US14015897

申请日：2013-08-30

Applicant: ARM Limited

Inventor： Sean Tristram Ellis ,  Jorn Nystad ,  Andreas Engh-Halstvedt

IPC: G06T1/20

CPC classification number: G06T15/005 ,  G06T11/40

Abstract: When processing a set of tiles to generate an output in a tile based graphics processing pipeline, the pipeline, for one or more tiles of the set of tiles, renders one or more render targets containing data to be used in a processing operation (602), and stores the render targets in the tile buffer (604). It also stores some but not all of the sampling position values for a render target or targets for use when processing an adjacent tile of the set of tiles (606). It then performs a processing operation for the tile using the stored render target or targets (608) and one or more stored sampling position values from another, adjacent tile of the set of tiles (610), to generate an output for the tile (612).

Abstract translation: 当处理一组瓦片以在基于瓦片的图形处理流水线中生成输出时，对于该瓦片组的一个或多个瓦片，流水线呈现包含要在处理操作（602）中使用的数据的一个或多个渲染目标， 并将渲染目标存储在瓦片缓冲器（604）中。 当处理一组瓦片（606）的相邻瓦片时，它还存储一些而不是所有的渲染目标的采样位置值或用于使用的目标。 然后，它使用存储的渲染目标或目标（608）和来自瓦片组（610）的另一个相邻瓦片的一个或多个存储的采样位置值来执行瓦片的处理操作，以生成瓦片（612）的输出 ）。

公开(公告)号：US20150046655A1

公开(公告)日：2015-02-12

申请号：US13962905

申请日：2013-08-08

Applicant: ARM Limited

Inventor： Jorn Nystad ,  Andreas Engh-Halstvedt

IPC: G06F12/08

CPC classification number: G06F12/0875 ,  G06F9/3004 ,  G06F9/3824 ,  G06F9/3828 ,  G06F9/3834 ,  G06F9/3851 ,  G06F9/3887 ,  G06F12/0815 ,  G06F12/0842 ,  G06T1/60

Abstract: A data processing system includes one or more processors 4, 5, 6, 7 operable to initiate atomic memory requests for execution threads and plural data caches 8, 9, 10, 11 that are used to store data needed to perform an atomic memory operation when an atomic memory operation is to be performed.When atomic operations are to be performed against a data cache, the results of atomic operations that are to access the same memory location are accumulated in a temporary cache line in the data cache pending the arrival in the cache of the “true” cache line from memory. The accumulated results of the atomic operations stored in the temporary cache line are then combined with the cache line from memory when the cache line arrives in the cache. Individual atomic values can also be reconstructed once the cache line arrives at the cache.

Abstract translation: 数据处理系统包括一个或多个处理器4,5,6,7，其可操作以发起用于执行线程的原子存储器请求以及用于存储执行原子存储器操作所需的数据的多个数据高速缓存8,9,10,11，当 将执行原子存储器操作。 当要针对数据高速缓存执行原子操作时，访问同一内存位置的原子操作的结果将累积在数据高速缓存中的临时高速缓存行中，等待到达“真”高速缓存行的高速缓存中 记忆。 然后，当高速缓存行到达缓存时，存储在临时高速缓存行中的原子操作的累积结果与来自存储器的高速缓存行组合。 一旦高速缓存行到达高速缓存，也可以重构单个原子值。