公开(公告)号：US20200034303A1

公开(公告)日：2020-01-30

申请号：US16142330

申请日：2018-09-26

Applicant: Arm Limited

Inventor： Radhika Sanjeev JAGTAP ,  Nikos NIKOLERIS ,  Andreas Lars SANDBERG ,  Stephan DIESTELHORST

IPC: G06F12/0864 ,  G06F12/1045

Abstract: Aspects of the present disclosure relate to an apparatus comprising a data array having locality-dependent latency characteristics such that an access to an open unit of the data array has a lower latency than an access to a closed unit of the data array. Set associative cache indexing circuitry determines, in response to a request for data associated with a target address, a cache set index. Mapping circuitry identifies, in response to the index, a set of data array locations corresponding to the index, according to a mapping in which a given unit of the data array comprises locations corresponding to a plurality of consecutive indices, and at least two locations of the set of locations corresponding to the same index are in different units of the data array. Cache access circuitry accesses said data from one of the set of data array locations.

公开(公告)号：US20180365142A1

公开(公告)日：2018-12-20

申请号：US15781979

申请日：2016-12-02

Applicant: Arm Limited

Inventor： Andreas Lars SANDBERG ,  Irenéus Johannes de JONG ,  Andreas Hansson

IPC: G06F12/02 ,  G06F11/10 ,  G06F3/06

Abstract: Broadly speaking, embodiments of the present technique provide an apparatus and methods for improved wear-levelling in non-volatile memory (NVM) devices. In particular, the present wear-levelling techniques operate on small blocks within a memory device, at a finer scale/granularity than that used by common wear-levelling techniques which often remap large blocks (e.g. several kilobytes) of data.

公开(公告)号：US20180157437A1

公开(公告)日：2018-06-07

申请号：US15806580

申请日：2017-11-08

Applicant: ARM LIMITED

Inventor： Andreas Lars SANDBERG ,  Nikos NIKOLERIS ,  David Hennah MANSELL

IPC: G06F3/06 ,  G06F12/10

CPC classification number: G06F3/0647 ,  G06F3/0611 ,  G06F3/0673 ,  G06F12/0831 ,  G06F12/10 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/1024

Abstract: An apparatus and method are provided for transferring data between address ranges in memory. The apparatus comprises a data transfer controller, that is responsive to a data transfer request received by the apparatus from a processing element, to perform a transfer operation to transfer data from at least one source address range in memory to at least one destination address range in the memory. A redirect controller is then arranged, whilst the transfer operation is being performed, to intercept an access request that specifies a target address within a target address range, and to perform a memory redirection operation so as to cause the access request to be processed without awaiting completion of the transfer operation. Via such an approach, the apparatus can effectively hide from the source of the access request the fact that the transfer operation is in progress, and hence the transfer operation can be arranged to occur in the background, and in a manner that is transparent to the software executing on the source that has issued the access request.

公开(公告)号：US20240346155A1

公开(公告)日：2024-10-17

申请号：US18299216

申请日：2023-04-12

Applicant: Arm Limited

Inventor： Roberto AVANZI ,  Andreas Lars SANDBERG ,  Ionut Alexandru MIHALCEA ,  David Helmut SCHALL ,  Alexander KLIMOV

IPC: G06F21/60 ,  G06F21/78

CPC classification number: G06F21/602 ,  G06F21/78

Abstract: Apparatuses and methods for memory protection are disclosed. A memory protection apparatus is interposed between a system cache and a memory system. The apparatus comprises encryption circuitry, which encrypts data item in dependence on encryption metadata and decrypts encrypted data items in dependence on the encryption metadata. In response to a change in a metadata item of the encryption metadata, when no cached copy of an affected data item is currently in the system cache, the affected data item is retrieved from the memory system, re-encrypted using the updated metadata item and returned to the memory system. When there is a cached copy, in dependence on update control data, the copy is retrieved from the system cache, encrypted using the updated metadata item and written out to the memory system.

公开(公告)号：US20220327009A1

公开(公告)日：2022-10-13

申请号：US17225674

申请日：2021-04-08

Applicant: Arm Limited

Inventor： Jonathan Curtis BEARD ,  Curtis Glenn DUNHAM ,  Andreas Lars SANDBERG ,  Roxana RUSITORU

IPC: G06F9/54 ,  G06F15/78 ,  G06F12/1009 ,  G06F12/02

Abstract: Message passing circuitry comprises lookup circuitry responsive to a producer request indicating message data provided on a target message channel by a producer node of a system-on-chip, to obtain, from a channel consumer information structure, selected channel consumer information associated with a given consumer node subscribing to the target message channel. Control circuitry writes the message data to a location associated with an address in a consumer-defined region of address space determined based on the selected channel consumer information. When an event notification condition is satisfied for the target message channel and the given consumer node, and an event notification channel is to be used, event notification data is written to a location associated with an address in a consumer-defined region of address space determined based on event notification channel consumer information associated with the event notification channel.

公开(公告)号：US20220188245A1

公开(公告)日：2022-06-16

申请号：US17593319

申请日：2020-01-03

Applicant: Arm Limited

Inventor： Andreas Lars SANDBERG ,  Stephan DIESTELHORST

IPC: G06F12/1009 ,  G06F12/0817

Abstract: A page table structure for address translation may include a relative type of page table entry, for which an address pointer to a next-level page table entry or a translated address may be specified using a relative offset value indicating an offset of the address pointer relative to a reference-point base address.

公开(公告)号：US20210224042A1

公开(公告)日：2021-07-22

申请号：US16745808

申请日：2020-01-17

Applicant: Arm Limited

Inventor： Andreas Lars SANDBERG ,  Matthias Lothar BOETTCHER

IPC: G06F7/72

Abstract: An apparatus and method are provided for maintaining a counter value. The apparatus has first counter control circuitry for maintaining a first counter value representing a first portion of a hybrid counter value, and second counter control circuitry for maintaining a second counter value representing a second portion of the hybrid counter value, wherein the second portion is a higher order portion of the hybrid counter value than the first portion. The first counter control circuitry is arranged to maintain the first counter value as a binary value that indicates a magnitude of the first counter value, the first counter control circuitry comprising adder circuitry that is responsive to an adjustment value to update the first counter value by performing an addition operation to add the adjustment value to a current binary value of the first counter value, and to generate a carry out signal which is set when a carry out is generated by the addition operation. The second counter control circuitry is arranged to maintain the second counter value as a bit sequence having N discrete states, and is responsive to the carry out signal being set to transition the second counter value from the current discrete state to a new discrete state. This allows an arbitrary value to be used as the adjustment value, that is smaller than or equal to the maximum value of the first counter, whilst avoiding the need for the generation and handling of carry bits to be managed across the entire bit range of the hybrid counter value.

公开(公告)号：US20210058237A1

公开(公告)日：2021-02-25

申请号：US16546596

申请日：2019-08-21

Applicant: Arm Limited

Inventor： Andreas Lars SANDBERG ,  Matthias Lothar BOETTCHER ,  Prakash S. RAMRAKHYANI

IPC: H04L9/06 ,  H04L9/32 ,  G06F12/14 ,  G06F21/72 ,  G06F13/16

Abstract: An apparatus and method are described, the apparatus comprising memory control circuitry configured to control access to data stored in memory, and memory security circuitry configured to generate encrypted data to be stored in the memory, the encrypted data being based on target data and a first one-time-pad (OTP). In response to an OTP update event indicating that the first OTP is to be updated to a second OTP different to the first OTP, the memory security circuitry is configured to generate a re-encryption value based on the first OTP and the second OTP, and the memory security circuitry is configured to issue a re-encryption request to cause updated encrypted data to be generated in a downstream component based on the encrypted data and the re-encryption value and to cause the encrypted data to be replaced in the memory by the updated encrypted data.

公开(公告)号：US20190155742A1

公开(公告)日：2019-05-23

申请号：US16169219

申请日：2018-10-24

Applicant: Arm Limited

Inventor： Prakash S. RAMRAKHYANI ,  Andreas Lars SANDBERG ,  Nikos NIKOLERIS ,  Stephan DIESTELHORST

IPC: G06F12/10

Abstract: There is provided an apparatus that includes an input address port to receive an input address from processor circuitry. Address storage stores a translation between the input address and an output address in an output address space. An output address port outputs the output address. An input data port receives data. Data storage stores the data. An output data port outputs the data stored in the data storage and control circuitry causes the data storage to store the translation between the input address and the output address. The control circuitry issues a signal to cause a page walk to occur in response to the input address being absent from the address storage and the data storage.

公开(公告)号：US20240078326A1

公开(公告)日：2024-03-07

申请号：US17903267

申请日：2022-09-06

Applicant: Arm Limited

Inventor： Brendan James MORAN ,  Adrian Laurence SHAW ,  Andreas Lars SANDBERG

IPC: G06F21/60 ,  G06F21/53

CPC classification number: G06F21/604 ,  G06F21/53

Abstract: An apparatus and method are described for providing a trusted execution environment. The apparatus comprises processing circuitry to execute program code, and interrupt controller circuitry, responsive to receipt of one or more interrupt requests, to select a given interrupt request from amongst the one or more interrupt requests, and to issue an interrupt signal to the processing circuitry identifying a given interrupt service routine providing program code to be executed by the processing circuitry to service the given interrupt request. The interrupt controller circuitry is responsive to the given interrupt request being a trusted execution environment (TEE) interrupt request, to issue the interrupt signal to identify as the given interrupt service routine a TEE interrupt service routine, and to inhibit issuance of any further interrupt signal until the TEE interrupt service routine has been executed by the processing circuitry. The interrupt controller circuitry comprises code protection circuitry to inhibit unauthorised modification of the TEE interrupt service routine, and data protection circuitry to inhibit unauthorised access to confidential data processed by the TEE interrupt service routine.