公开(公告)号：US12118088B2

公开(公告)日：2024-10-15

申请号：US16855716

申请日：2020-04-22

Applicant: Arm Limited

Inventor： Subbayya Chowdary Yanamadala ,  Jeremy Patrick Dubeuf ,  Carl Wayne Vineyard ,  Matthias Lothar Boettcher ,  Hugo John Martin Vincent ,  Shidhartha Das

IPC: G06F21/56 ,  G06F9/54 ,  G06F21/72 ,  G06F21/85

CPC classification number: G06F21/566 ,  G06F9/54 ,  G06F21/72 ,  G06F21/85 ,  G06F2221/034

Abstract: A moderator system that can receive outputs of various stages of the security analytic framework and can receive input from external sources to provide information about emerging styles of attacks. One or more models/behavioral profiles can be curated by the moderator system, and the moderator system can provide updates to components of the security analytics framework.

公开(公告)号：US11232196B2

公开(公告)日：2022-01-25

申请号：US16409205

申请日：2019-05-10

Applicant: Arm Limited

Inventor： Carl Wayne Vineyard ,  Christopher Neal Hinds ,  Subbayya Chowdary Yanamadala ,  Asaf Shen

IPC: G06F21/55 ,  G06F21/56

Abstract: A computing device can include a comparator coupled to an I/O pin of the computing device; a storage unit coupled to the comparator; and a counter coupled to receive an output of the comparator, an output of the counter being coupled to a computation engine to provide a limit-exceeded signal to the computation engine, wherein the counter comprises a volatile counter and a nonvolatile storage, wherein the nonvolatile storage stores a bit for each top volatile count number of events identified by the volatile counter. The computing device can further include a backup power source coupled to the volatile counter; and readout circuitry and control logic coupled to the volatile counter and to the nonvolatile storage, the readout circuitry and control logic being configured to control operations of the volatile counter during an error event and determine a total number of events. The computing device can be a smart card.

公开(公告)号：US10997322B2

公开(公告)日：2021-05-04

申请号：US15967900

申请日：2018-05-01

Applicant: Arm Limited

Inventor： Adeline-Fleur Fleming ,  Carl Wayne Vineyard ,  George Mcneil Lattimore ,  Christopher Neal Hinds ,  Robert John Harrison ,  Mikael Rien ,  Abdellah Bakhali ,  Robert Christiaan Schouten ,  Jean-Charles Bolinhas

IPC: G06F21/75 ,  H02J7/00 ,  H03K5/24 ,  H01L27/00 ,  H02J7/34 ,  H03K17/687 ,  H03K3/03

Abstract: An apparatus is provided to enable power supply input to be isolated from power supply output. Power is received from a first power signal at a first of a plurality of charge stores. A second power signal is output from a second of the plurality of charge stores. The second power signal is isolated from the first power supply. The first charge store can be charged from the power input whilst isolated from the power output. The second charge store can be discharged to the power output, while isolated from the power input.

公开(公告)号：US20210097173A1

公开(公告)日：2021-04-01

申请号：US16584865

申请日：2019-09-26

Applicant: Arm Limited

Inventor： Joshua Randall ,  Joel Thornton Irby ,  Carl Wayne Vineyard ,  Mudit Bhargava

IPC: G06F21/55 ,  H03K19/003 ,  G11C13/00

Abstract: Various implementations described herein refer to a method for tracking abnormal incidents while monitoring activity of logic circuitry. The method may include detecting a tamper event related to the abnormal incidents and storing an attack signature related to the tamper event. The attack signature may be stored in non-volatile memory (NVM), such as, e.g., correlated electron random access memory (CeRAM).

公开(公告)号：US20170364710A1

公开(公告)日：2017-12-21

申请号：US15185789

申请日：2016-06-17

Applicant: ARM Limited

Inventor： Bal S. Sandhu ,  George McNeil Lattimore ,  Carl Wayne Vineyard

IPC: G06F21/75 ,  H04L9/00

CPC classification number: G06F21/75 ,  G09C1/00 ,  H04L9/003 ,  H04L2209/125

Abstract: An apparatus for obfuscating power consumption associated with one or more operations of a logic circuitry of a processor. The apparatus comprises counterbalance circuitry configured to provide a second power consumption to directly counterbalance the power consumption associated with the one or more operations of the logic circuitry. The second power consumption varies inversely with the power consumption associated with the one or more operations of the logic circuitry. The apparatus further comprises header circuitry configured to enable a common node to vary in voltage corresponding to the one or more operations of the logic circuitry. The counterbalance circuitry and the header circuitry are each coupled to the logic circuitry at the common node.