公开(公告)号：US20200126619A1

公开(公告)日：2020-04-23

申请号：US16167822

申请日：2018-10-23

Applicant: Arm Limited

Inventor： Akhilesh Ramlaut Jaiswal ,  Mudit Bhargava ,  George McNeil Lattimore

IPC: G11C14/00 ,  G11C11/419 ,  G11C5/14 ,  G11C5/06

Abstract: Briefly, embodiments of claimed subject matter relate to backup of parameters, such as binary logic values, stored in nonvolatile memory, such as one or more SRAM cells. Binary logic values from a SRAM cell, for example, may be stored utilizing resistance states of a magnetic random-access memory (MRAM) element. Parameters stored in one or more MRAM elements may be restored to SRAM memory cells following a backup.

公开(公告)号：US11188682B2

公开(公告)日：2021-11-30

申请号：US16378256

申请日：2019-04-08

Applicant: ARM Limited

Inventor： Bal S. Sandhu ,  George McNeil Lattimore ,  Carl Wayne Vineyard

IPC: H04L29/06 ,  G06F21/75 ,  G06F1/28

Abstract: An apparatus for masking power consumption associated with one or more operations of a logic circuitry of a processor. The apparatus comprises power-complementing circuitry configured to provide a second power consumption to directly power-complementing the power consumption associated with the one or more operations of the logic circuitry. The second power consumption complements the power consumption associated with the one or more operations of the logic circuitry. The apparatus further comprises header circuitry configured to enable a common node to vary in voltage corresponding to the one or more operations of the logic circuitry. The power-complementing circuitry and the header circuitry are each coupled to the logic circuitry at the common node.

公开(公告)号：US11004479B2

公开(公告)日：2021-05-11

申请号：US16833154

申请日：2020-03-27

Applicant: Arm Limited

Inventor： Mudit Bhargava ,  Shidhartha Das ,  George McNeil Lattimore ,  Brian Tracy Cline

IPC: G11C5/06 ,  G11C14/00 ,  G11C8/10 ,  G11C13/00

Abstract: Disclosed are methods, systems and devices for operation of memory device. In one aspect, volatile memory bitcells and non-volatile memory bitcells may be integrated to facilitate copying of memory states between the volatile and non-volatile memory bitcells.

公开(公告)号：US20210090653A1

公开(公告)日：2021-03-25

申请号：US16582743

申请日：2019-09-25

Applicant: Arm Limited

Inventor： Fernando Garcia Redondo ,  Shidhartha Das ,  Glen Arnold Rosendale ,  George McNeil Lattimore ,  Mudit Bhargava

IPC: G11C13/00

Abstract: In a particular implementation, a method includes: providing a first voltage to a word-line coupled to a first transistor device; providing a second voltage to a bit-line coupled to the first transistor device; providing a third voltage to a source-line coupled between a programmable resistive device and a voltage control element. Also, the first transistor device is coupled to the programmable resistive device and the voltage control element, where the programmable resistive device is configured to replace a first data value by writing a second data value in the programmable resistive device. Moreover, in response to a voltage difference across the programmable resistive device exceeding a particular threshold, limiting the voltage difference by one of reducing the second voltage on the bit-line or increasing the third voltage on the source-line.

公开(公告)号：US10741246B2

公开(公告)日：2020-08-11

申请号：US15960365

申请日：2018-04-23

Applicant: Arm Limited

Inventor： Mudit Bhargava ,  Brian Tracy Cline ,  George McNeil Lattimore ,  Bal S. Sandhu

IPC: G11C11/00 ,  G11C14/00 ,  G11C7/06 ,  G11C13/00

Abstract: Disclosed are methods, systems and devices for operation of memory device. In one aspect, volatile memory bitcells and non-volatile memory bitcells may be integrated to facilitate transfer of stored values between the volatile and non-volatile memory bitcells.

公开(公告)号：US10607659B2

公开(公告)日：2020-03-31

申请号：US15960405

申请日：2018-04-23

Applicant: Arm Limited

Inventor： Mudit Bhargava ,  Shidhartha Das ,  George McNeil Lattimore ,  Brian Tracy Cline

IPC: G11C5/06 ,  G11C14/00 ,  G11C8/10 ,  G11C13/00

Abstract: Disclosed are methods, systems and devices for operation of memory device. In one aspect, volatile memory bitcells and non-volatile memory bitcells may be integrated to facilitate copying of memory states between the volatile and non-volatile memory bitcells.

公开(公告)号：US11520658B2

公开(公告)日：2022-12-06

申请号：US16669906

申请日：2019-10-31

Applicant: Arm Limited

Inventor： Joel Thornton Irby ,  Wendy Arnott Elsasser ,  Mudit Bhargava ,  Yew Keong Chong ,  George McNeil Lattimore ,  James Dennis Dodrill

IPC: G06F11/10 ,  G11C5/14 ,  G11C7/10 ,  G11C29/12 ,  G06N20/00

Abstract: A system-on-chip is provided that includes functional circuitry that performs a function. Control circuitry controls the function based one or more configuration parameters. Non-volatile storage circuitry includes a plurality of non-volatile storage cells each being adapted to write at least a bit of the one or more configuration parameters in a rewritable, persistent manner a plurality of times. Read circuitry locally accesses the non-volatile storage circuitry, obtains the one or more configuration parameters from the non-volatile storage circuitry and provides the one or more configuration parameters to the control circuitry. Write circuitry obtains the one or more configuration parameters and provides the one or more configuration parameters to the non-volatile storage circuitry by locally accessing the non-volatile storage circuitry.

公开(公告)号：US10958266B2

公开(公告)日：2021-03-23

申请号：US16600366

申请日：2019-10-11

Applicant: Arm Limited

Inventor： Bal S. Sandhu ,  George McNeil Lattimore ,  Robert Campbell Aitken

IPC: H03K17/14 ,  G11C13/00 ,  G11C29/02 ,  H01L45/00 ,  H01L49/00

Abstract: Subject matter disclosed herein may relate to programmable current for correlated electron switches.

公开(公告)号：US10854291B2

公开(公告)日：2020-12-01

申请号：US16167822

申请日：2018-10-23

Applicant: Arm Limited

Inventor： Akhilesh Ramlaut Jaiswal ,  Mudit Bhargava ,  George McNeil Lattimore

IPC: G11C14/00 ,  G11C5/06 ,  G11C5/14 ,  G11C11/419

Abstract: Briefly, embodiments of claimed subject matter relate to backup of parameters, such as binary logic values, stored in nonvolatile memory, such as one or more SRAM cells. Binary logic values from a SRAM cell, for example, may be stored utilizing resistance states of a magnetic random-access memory (MRAM) element. Parameters stored in one or more MRAM elements may be restored to SRAM memory cells following a backup.

公开(公告)号：US20170364710A1

公开(公告)日：2017-12-21

申请号：US15185789

申请日：2016-06-17

Applicant: ARM Limited

Inventor： Bal S. Sandhu ,  George McNeil Lattimore ,  Carl Wayne Vineyard

IPC: G06F21/75 ,  H04L9/00

CPC classification number: G06F21/75 ,  G09C1/00 ,  H04L9/003 ,  H04L2209/125

Abstract: An apparatus for obfuscating power consumption associated with one or more operations of a logic circuitry of a processor. The apparatus comprises counterbalance circuitry configured to provide a second power consumption to directly counterbalance the power consumption associated with the one or more operations of the logic circuitry. The second power consumption varies inversely with the power consumption associated with the one or more operations of the logic circuitry. The apparatus further comprises header circuitry configured to enable a common node to vary in voltage corresponding to the one or more operations of the logic circuitry. The counterbalance circuitry and the header circuitry are each coupled to the logic circuitry at the common node.